Top Design Engineers in Austin, Texas

Hooi-Min Lim

SMTS System Design Engineer

Austin, Texas

SMTS System Design Engineer

Equipment Engineer

Coventry University

Recommendations: 12

Verilog

Microprocessors

Hardware Design

Processors

Debugging

Computer Architecture

FPGA

Xilinx

Ananth Chellappa

Analog Design Engineer

Austin, Texas

Analog Design Engineer

Design Engineer

Senior Analog Design Engineer

Design Engineer

Design Intern

Analog Design Engineer

IC Design Engineer

Senior IC Design Engineer

Georgia Institute of Technology

Indian Institute of Technology, Madras

St. Joseph's Boys High School

Recommendations: 10

Microcontrollers

Mixed Signal

Analog Circuit Design

Cadence

Integrated Circuit Design

Circuit Design

Perl

Sagar Bhogela

Senior Design Engineer

Austin, Texas

Senior Design Engineer

CPU Design Engineer

Logic Design Intern

SoC Design Engineer

Interim Intern

Staff Engineer

Texas A&M University

Indian Institute of Technology, Kharagpur

Recommendations: 9

Verilog

Matlab

SoC

RTL design

VHDL

Linux

Microprocessors

Sreenivasan Kandagatla

Design Engineer

Austin, Texas

Design Engineer

Senior Design Engineer

Verification Engineer

Design Engineering Architect

Lead Engineer

Verification Engineer

College of Engineering Pune

Jawaharlal Nehru Technological University

Saketha Junior College

Recommendations: 9

Functional Verification

Specman

SoC

Memory Controller

DDR Technology

Debugging

VLSI

ASIC

Phanendra Gunturi

Sr.Engineer

Austin, Texas

Sr.Engineer

Application Engineer

Senior Member Of Technical Staff

Sr.Physical Design Engineer

Coventry University

University of Hyderabad

Recommendations: 8

Logic Synthesis

Static Timing Analysis

Formal Verification

Physical Design

Integrated Circuit Design

TCL

Functional ECO Implementation

EDA

Luai Abou-Emara

Principal Physical Design Engineer

Austin, Texas

Principal Physical Design Engineer

Senior Staff Engineer

Walden University

University of Washington

Recommendations: 6

Physical Design

Timing Closure

TCL

Perl

Low-power Design

Primetime

EDI

Redhawk

l****[email protected]

Manish Aggarwal

Analog Designer

Austin, Texas

Analog Designer

Senior Analog and Mixed Signal Design Engineer

Analog Designer

Sr. Analog and Mixed Signal Designer

University of Minnesota-Twin Cities

Punjab Engineering College

Recommendations: 6

Verilog

Analog Circuit Design

VLSI

Integrated Circuit Design

Semiconductors

Hardware

Static Timing Analysis

Business Strategy

Abhas Borkar

Principal Solutions Engineer

Austin, Texas

Principal Solutions Engineer

Hardware Design Staff Engineer

Teaching Assistant and Graduate Student

Hardware Design Engineer

Senior Physical Design Engineer

Hardware Design Staff Engineer

Design Engineer - II

Design Engineer

Cornell University

Netaji Subhas Institute of Technology (DIT)

Recommendations: 6

Set Top Box

Software Development

Verilog

SoC

EDA

Static Timing Analysis

TCL

Embedded Systems

Andrew Pua

Product Development Engineer – PCD

Austin, Texas

Product Development Engineer – PCD

Principal Physical Design Engineer

Utah State University

Recommendations: 6

Physical Design

Balaji Subbiah

Supply Chain and Operations, Americas NPI Launch Readiness

Austin, Texas

Supply Chain and Operations, Americas NPI Launch Readiness

Manager - eCommerce Category Management/Vendor Management

Global Program Manager - NPI

Manager - Product Development/Management

Senior Engineer - Product Operations

Customer Support Leader - Service Operations

Design Engineer

Wayne State University

Anna University

Balalok Secondary School

Recommendations: 6

Pro/Engineer

Product Development

Manufacturing

FMEA

DFMEA

SPC

Minitab

Solidworks

Tushar Agarwal

Design Verification Engineer

Austin, Texas

Design Verification Engineer

ASIC Design Verification Engineer

Sr. Research & Development Engineer

Design Verification Engineer

Resarch Assistant

Research Assistant

Design Engineer

Design Verification Engineer

Portland State University

RAIT

Shreeram Polytechnic

Recommendations: 5

SystemVerilog

Verilog

VHDL

Functional Verification

Perl

Debugging

EDA

Verification

Lucie Nechanicka

Sr. Physical Design Engineer

Austin, Texas

Sr. Physical Design Engineer

SOC Physical Design Engineer

Design Engineer

Sr. Design Engineer

Staff Integration Engineer

SOC Physical Design Engineer

Hogeschool West-Vlaanderen - Vlaamse Autonome Hogeschool

Czech Technical University in Prague

Gymnazium Voderadska

Recommendations: 5

Primetime

Functional Verification

Clock Tree Synthesis

Timing

Integrated Circuit Design

RTL coding

Physical Synthesis

Noise

l****[email protected]

Sridhar Gudibanda

Senior Staff Engineer/Manager

Austin, Texas

Senior Staff Engineer/Manager

Staff Engineer/Manager

Staff Engineer

Senior Hardware Engineer

Design Verification Engineer

Component Design Engineer

Design Engineer

DAAD Exchange Student

Indian Institute of Technology, Kharagpur

National Institute of Technology Warangal

Technische Universität Berlin

Recommendations: 5

FPGA

Debugging

SystemVerilog

GPU

OpenCL

DirectX

OpenGL

OVM/VMM/RVM

Shardendu Shekhar

Design Engineer

Austin, Texas

Design Engineer

ASIC Engineer

Design Engineer 2

Co-Op Engineer

Student

The University of Texas at Dallas

Bangalore Institute of Technology

Recommendations: 5

Integrated Circuit...

SPICE

Logic Design

Formal Verification

Static Timing Analysis

Cadence Virtuoso

LEC

Verilog

James Breaux

Industrial Design Intern

Austin, Texas

Industrial Design Intern

Senior Designer

Industrial & UX/UI Designer

Industrial Designer

Bicycle Mechanic

Field Claim Specialist

Director of Product

Industrial Designer

Industrial Design Engineer

University of Louisiana at Lafayette

Recommendations: 5

Product Design

Sketching

Design Thinking

Industrial Design

Product Development

Illustrator

Photoshop

Concept Generation

Balasubramaniam Narayan

Design Verification Engineer

Austin, Texas

Design Verification Engineer

Senior Hardware Design Engineer

Design Engineer -1

Intern

ASIC verification engineer

Senior Design Verification Engineer

Verification Engineer

R&D Engineer 2

Component Design Engineer

Birla Institute of Technology and Science, Pilani

SBOA

CSI Ewarts

Recommendations: 4

SystemVerilog

Verilog

Perl

Functional Verification

VCS

Formal Verification

VMM

Open Verification Methodology

Alexander Grobman

Verification Engineer

Austin, Texas

Verification Engineer

SOC Senior Verification Engineer

Staff design verification engineer

Design Verification Engineer

Senior verification engineer

Senior Design Engineer

Design Engineer

Moscow Technical University of Communications and Informatics (MTUCI)

Moscow Institute of Electronics and Mathematics (Technical University)

Recommendations: 4

Verilog

Firmware

Assembly

Perl

Linux

SoC

Logic Design

Microcontrollers

Anand Acharya

VLSI Design Engineer

Austin, Texas

VLSI Design Engineer

Design Verification Consultant

Project Engineer

Design Verification Engineer

Engineer, Staff

University of California, San Diego

Ramrao Adik Institute of Technology, Mumbai

Recommendations: 4

Verilog

SystemVerilog

SoC

C/C++

Embedded Systems

ASIC Design Verification

ARM

Functional Verification

Mark Arita

Software Validation Engineer

Austin, Texas

Software Validation Engineer

Software Test Design Engineer

Senior Software Engineer

Software Development Engineer

Senior Software Engineer

Georgia Institute of Technology

Oregon State University

Recommendations: 4

Testing

Test Automation

Programming

Scrum

Operating Systems

Java

Android Development

Paul Bassett

Senior Engineer

Austin, Texas

Senior Engineer

Sr IC Design Engineer

Senior Engineer

AMD Fellow

Sr Director, Technology

Senior IC Design Engineer

AMD Fellow

Principal Engineer

Sr IC Design Engineer

Massachusetts Institute of Technology

Texas A&M University

Recommendations: 4

Debugging

EDA

Embedded Systems

Engineering Management

Integrated Circuit Design

Integration

Microprocessors

Ravinder Andrew

Architect

Austin, Texas

Architect

VLSI Design Engineer

Oregon Health and Science University

Osmania University

Government Institute of Electronics

Recommendations: 4

VLSI

Circuit Design

Intel

Semiconductors

SoC

Timing

Static Timing Analysis

Natalie Hill

Web and Content Producer

Austin, Texas

Web and Content Producer

Senior Interaction Designer

Mobile Interaction Design Associate

Sr. UX Design Engineer

User Experience Designer

Web Designer

Associate Web Designer

Senior Content Strategist (Contract)

Web and UX Designer

Teaching Assistant

Web Producer

Interaction Designer (Contract)

The University of Texas at Austin

University of California, Los Angeles

Columbia College Chicago

Recommendations: 4

HTML

Editing

Marketing

Logo Design

Digital Recording

Interaction Design

CMS

Information Architecture

n****[email protected]

Joel Feldman

Sr ASIC Verification Engineer

Austin, Texas

Sr ASIC Verification Engineer

Sr Staff Design Verification Engineer

Sr Field Applications Engineer

Rotational Engineer

Sr VLSI Design Engineer

Rochester Institute of Technology

National Technological University

Recommendations: 4

UVM

OVM

SoC

RTL Verification

Hardware Verification

SystemVerilog

Technical Training

Open Verification Methodology

Hermes Gonzalez

Test Design Engineer

Austin, Texas

Test Design Engineer

Website Designer and Developer

Electrical Engineer Contractor

Software/Electrical Engineer

Firmware Engineer Contractor

Embedded Software Engineer

The University of Texas at Austin

S. F. Austin High School

Recommendations: 4

Labview

PCB design

Test Equipment

Software Design

Systems Engineering

Electronics

John Xu

Senior Director of Engineering

Austin, Texas

Senior Director of Engineering

IP Design Manager, NMG

VP HW R&D

Founder and CEO

Member of Technical Staff

SOC Design Manager, NMG

Senior Member Technical Staff, PowerPC SOC Architect

Systems and Architecture Director, DNG

Senior Design Engineer

CTO

The University of Texas at Austin

Rensselaer Polytechnic Institute

University of Science and Technology of China

Recommendations: 4

SoC

Codecs

DSL

ASIC

Embedded Systems

Project Management

Engineering Management

z****[email protected]

Jacob Liu

SEG SoC DFT Engineer

Austin, Texas

SEG SoC DFT Engineer

SEG Wireless SOC & RF Engineer

MTS ASIC/ Layout Design Engineer

Sr. ASIC/ Layout Design Engineer

Hardware Engineer

ASIC Engineer

Dalian University of Technology

Xi'an Jiaotong University

Recommendations: 3

FPGA

Xilinx

RTL design

Altera

Embedded Systems

ASIC

Verilog

Semiconductors

Anthony Louviere

IC Design Engineer

Austin, Texas

IC Design Engineer

Lead Hardware Design Engineer

Senior IC Design Engineer

IC Design Engineer

The University of Texas at Austin

Louisiana State University

Recommendations: 3

VHDL

Verilog

Hspice

HSIM

Perl

Spectre

Cadence Virtuoso

l****[email protected]

Art Arizpe

Senior ASIC Design Engineer

Austin, Texas

Senior ASIC Design Engineer

Distinguished Engineer

ASIC Developer

Member of the Technical Staff

Team Leader/Senior Engineer

Senior Manager

Engineer Consultant

Senior Engineer/HW Architect

Founder, Vice-President Engineering, Director of Engineering, Senior Engineer

Director of HW Engineering

Project Manager/Engineering Manager

Project Leader/Design Engineer

Design Engineer

Recommendations: 3

SoC

Product Development

Networking

Acceleration

System Architecture

Engineering Management

Technical Project...

Defining Product...

Will Hong

Sr. Engineering Manager, HW/SW Platforms

Austin, Texas

Sr. Engineering Manager, HW/SW Platforms

Hardware Engineer

Design Engineer

Microprocessor Validation Engineer

Digital Design Engineer

Staff Design Engineer/Manager of Mixed-Signal Methodology

Staff Design Engineer

Principal Solutions Engineer

Design Engineer

Member of Technical Staff

The University of Texas at Austin

University of Illinois at Urbana-Champaign

Recommendations: 3

ASIC

SoC

RTL Design

Verilog

SystemVerilog

EDA

Mixed Signal

Debugging

w****[email protected]

Bryant Sorensen

Manager, DSP Platforms

Austin, Texas

Manager, DSP Platforms

DSP Software Group Leader

Principal Firmware Engineer

Principal DSP Firmware Engineer

Research Assistant

Firmware Engineering Lead

DSP Group Leader

Principal Engineer and Owner

Sr. DSP Engineer

Sr. DSP Design Engineer

Principal DSP Engineer

University of Tennessee Space Institute

Utah State University

Recommendations: 3

Digital Design

Numerical Analysis

DSP

Firmware

ASIC

Embedded Systems

PCB design

Signal Processing

Anurag Jindal

Staff DFT Engineer

Austin, Texas

Staff DFT Engineer

Director, SOC DFT (Automotive)

Senior Design Engineer

Design Manager - DFT

Thapar Institute of Engineering and Technology

Recommendations: 3

DFT

ATPG

Scan

LBIST

MBIST

JTAG

Fastscan

Tetramax

Dhruba Dutta

Analog IC Design Engineer

Austin, Texas

Analog IC Design Engineer

Graduate Teaching Assistant

Analog/RF IC Design Engineer

Undergraduate Teaching Assistant

Intern

Arizona State University

IIIT Hyderabad

Recommendations: 3

RF Circuit Design

Analog Circuit Design

Cadence Virtuoso

Cadence Spectre

Cadence Virtuoso Layout Editor

High Speed I/O Design

Mixed Signal

Matlab

David Rackley

Design Center Manager

Austin, Texas

Design Center Manager

Physical Design Engineer

Sr SOC Design Engineer

Application Engineer Sr. Staff, Physical Design

The University of Texas at Dallas

University of Texas at Austin

Recommendations: 3

SoC

Verilog

Semiconductors

VLSI

Static Timing Analysis

Embedded Systems

DFT

Logic Synthesis

Shrihari Achayath

Senior Design Engineer

Austin, Texas

Senior Design Engineer

VLSI Project Engineer

Physical Design Engineer

Staff AE , Logic Libraries

Model Engineering College , Kochi

Technical higher seconday school,Vattamkulam

Recommendations: 3

Perl

Physical Design

Compilers

Timing Closure

EDA

ASIC

TCL

Rogelio Hernandez

Sr. Layout Design Engineer

Austin, Texas

Sr. Layout Design Engineer

Jr. Layout Design Engineer

Sr. Layout Design Engineer

Design Engineer

Research Assistant at VLSI group in the electrical and computer department

IC Layout Engineer

Mask Design Engineer

Research Assistant

Benemerita Universidad Autonoma de

Recommendations: 3

Mixed Signal

Circuit Design

FPGA

Semiconductors

ASIC

Verilog

EDA

Peter Droppa

Member of Technical Staff

Austin, Texas

Member of Technical Staff

Principal Engineer

Staff Design Engineer

University of Illinois at Urbana-Champaign

Recommendations: 2

Testing

Test Automation

Test Planning

Semiconductor Manufacturing

Java

XML

Performance Testing

Cost Reduction

Akarsh Hebbar

CPU Micro-Architect

Austin, Texas

CPU Micro-Architect

Research Intern

Graduate Research Assistant [Computer Architecture]

Design Engineer

CPU Architect/Logic design

PSU

Visvesvaraya Technological University

Recommendations: 2

Computer Architecture

Microarchitecture

Logic Design

RTL design

Debugging

Microprocessors

Hardware Design

Functional Verification

Suresh Thapa

FPGA Design Engineer

Austin, Texas

FPGA Design Engineer

Sr. FPGA Design Engineer

Test Engineer

Staff FPGA Design Engineer

Master Technologist, FPGA Design Engineer

High School Tech Ed Teacher

Sr. ASIC Design Engineer

Southern Illinois University Edwardsville

National Institute of Technology Warangal

Recommendations: 2

Hardware Architecture

Verilog

FPGA

Debugging

ASIC

Linux

VHDL

Testing

Mohit Arora

Design Engineer

Austin, Texas

Design Engineer

Director, Architecture for low power MPUs

Principal Security Architect

Sr. Systems and Security Architect

Sr. Design Architect and Security Lead

Design Lead and Architect

Member Technical Staff

Design Engineer

Senior Systems Engineer and Security Architect(SMTS)

Netaji Subhas Institute of Technology

Cambridge school delhi

Recommendations: 2

SoC

Verilog

Semiconductors

Embedded Systems

USB

ASIC

VLSI

Microcontrollers

Joel Davidson

ASIC Design Engineer

Austin, Texas

ASIC Design Engineer

Senior Engineer

Design Consultant

Embedded Software Engineer

System Design Engineer

Senior Design Engineer

MTS

Advisory Engineer

RTL Design Engineering Consultant

Cornell University

Recommendations: 2

Verilog

Perl

Embedded Systems

Assembly

SoC

ASIC

Semiconductors

j*****@prismnet.com

Ali Naderi

Postdoctoral Fellow

Austin, Texas

Postdoctoral Fellow

Analog IC Design Engineer

Analog/Mixed Signal IC Design Engineer

ADC Circuit Design Engineer

Research Associate

Analog IC Design Engineer

École Polytechnique de Montréal

Urmia University

Iran University of Science and Technology

Recommendations: 2

Mixed Signal

ADCs

Analog Circuit Design

Circuit Design

Analog Filters

Semiconductors

Cadence Virtuoso

Error Correction

n****[email protected]

Sameer Majithia

DSP- Software Engineer

Austin, Texas

DSP- Software Engineer

Sr Verification Engineer

Interim Engineering Intern

Design Engineer - 2

Design Verification Engineer

Staff Engineer

North Carolina State University

Pune Institute of Computer Technology

Recommendations: 2

ASIC

Computer Architecture

Verilog

SystemVerilog

Debugging

Functional Verification

Digital Signal Processors

Srikanth Dwarakanath

Hardware Engineer

Austin, Texas

Hardware Engineer

CPU RTL Design Engineer

Intern

CPU RTL Design Engineer

On-Chip Fabric Design Engineer

CPU RTL Design Engineer

SoC RTL Design Engineer

Georgia Institute of Technology

Recommendations: 2

Verilog

C++

Cadence Virtuoso

ModelSim

SystemVerilog

Computer Architecture

Unix

Gokulakrishnan Manoharan

Senior Member Technical Staff at MediaTek

Austin, Texas

Senior Member Technical Staff at MediaTek

Lead Engineer

Senior Design Engineer

Design Engineer

Member Technical Staff

Birla Institute of Technology and Science

College of Engineering, Guindy

Recommendations: 2

g****[email protected]

Darren Terry

Security Engineer

Austin, Texas

Security Engineer

Sr. Staff, Security System Design Engineer

Security Engineering & CSIRT Team Lead

Network Security Engineer

Network Security Analyst

Unix Systems Administrator & Network Engineer

Old Dominion University

Recommendations: 2

Perl

Linux

Red Hat Linux

Windows System...

Cisco IOS

SIEM

RSA SecurID

Websense

Vinayak Kamath

Senior Design Engineer

Austin, Texas

Senior Design Engineer

Co-op Engineer

Summer Intern

IC Design Engineer

Intern

Member Of Technical Staff

Senior Design Engineer

Research Assistant

University of California, Santa Barbara

UC Santa Barbara

National Institute of Technology Karnataka

Recommendations: 1

Verilog

VLSI

RTL design

Testing

Debugging

Validation

Perl

Static Timing Analysis

k****[email protected]

Ritukar Khanna

Staff Engineer

Austin, Texas

Staff Engineer

Electrical Engineer

Staff Engineer

Senior Design Engineer

University of Southern California

Vellore Institute of Technology

Little Flower Junior College

Recommendations: 1

Verilog

VHDL

C++

SystemVerilog

Unix

Open Verification Methodology

VCS

VLSI

Sandeep Gupta

CSSI Fellow (Center for Silicon System Implementation)

Austin, Texas

CSSI Fellow (Center for Silicon System Implementation)

Summer Intern

Summer Research Intern

Senior Logic Design Engineer

Graduate Teaching Assistant: 18-721 Advanced Analog IC design

Graduate Teaching Assistant: 18-623 Analog IC design

Carnegie Mellon University

Indian Institute of Technology, Kanpur

Recommendations: 1

Microarchitecture

RTL coding

Logic Design

Static Timing Analysis

Digital Electronics

VLSI

Verilog

Bob Renninger

Senior RF IC Design Engineer

Austin, Texas

Senior RF IC Design Engineer

Member of Technical Staff

Analog IC Design Engineer

Senior Member of Technical Staff

Senior Analog IC Design Engineer

Senior Member of Technical Staff

University of Arkansas at Little Rock

Michigan State University

Recommendations: 1

Mixed Signal

Analog

Analog Design

PLL

Integrated Circuit Design

Cadence Virtuoso

Analog Circuit Design

Yashpal Makkar

Sr Engineer

Austin, Texas

Sr Engineer

Design Engineer

Sr. Verification Engineer

Sr. Staff Design Verification Enginner

Sr. Staff Engineer - Digital

Engineer/Scientist

Principal Engineer

Sr. Consulting Engineer

Sr. Enginner

Maharshi Dayanand University

Modern Vidya Niketan

Dayanand Public School, Sec-14

Recommendations: 1

Functional Verification

Emulation

Open Verification Methodology

Cadence

Set Top Box

SoC

ASIC

Hardware

y****[email protected]

Kumar Abhishek

Design Engineer

Austin, Texas

Design Engineer

Delhi College of Engineering

Recommendations: 1

Mixed Signal

Analog Circuit Design

Power Management

Low-power Design

Analog

SPICE

Digital Circuit Design

Verilog-AMS modeling

k****[email protected]

Evan Hamamcy

Mfg. Engineer, Product Engineer and Customer Quality Engineer

Austin, Texas

Mfg. Engineer, Product Engineer and Customer Quality Engineer

Customer Program Manager

Design Engineer, Mfg. Engineer and Buyer

The University of Texas at Austin - Red McCombs School of Business

The University of Texas at Austin

Recommendations: 1

e****[email protected]

Rajesh Challa

Manager/Staff Memory Design Engineer

Austin, Texas

Manager/Staff Memory Design Engineer

Sr. R&D Engineer II

Design Engineer

Internship

Teaching Assistant

Research Assistant

University of Louisiana at Lafayette

Jawaharlal Nehru Technological University

Recommendations: 1

Static Timing Analysis

Verilog

VHDL

VLSI

Compilers

Circuit Analysis

Integrated Circuit...

ASIC

Arnab Dutta

Senior Staff Engineer

Austin, Texas

Senior Staff Engineer

Associate Staff Design Engineer

Student

Analog Design Engineer 2

Teaching Assistant

Product Engineer Intern

Staff Engineer

Hardware Engineer(Analog)

Analog Design Engineer 3

Senior Analog/Mixed Signal Design Engineer

Hardware Engineer

Student

The University of Texas at Austin

IIT Kharagpur

Recommendations: 1

Mixed Signal

Circuit Design

SPICE

Logic Design

Cadence Virtuoso

Verilog

Low-power Design

Matlab

Joshy Mathew

Senior Design Engineer

Austin, Texas

Senior Design Engineer

Tech Lead

Senior Design Engineer

Model Engineering College

St. Thomas HSS Pala

Recommendations: 1

Physical Design

Timing Closure

Power Integrity

Signal Integrity

Physical Verification

TCL

VLSI

ASIC

Essam Atalla

Associate Staff Analog/Mixed-Signal Design Engineer

Austin, Texas

Associate Staff Analog/Mixed-Signal Design Engineer

Design Engineer

Radio Design Lead and Staff RFIC Design Engineer

Staff Design Engineer

Design Engineering Manager

Senior Mixed-Signal Design Engineer

RFIC Design Engineer

Design Intern

Teaching and Research Assistant

The University of Texas at Dallas

Ain Shams University

Recommendations: 1

Analog Circuit Design

Mixed Signal

VLSI

Integrated Circuit Design

Simulations

Matlab

Circuit Design

e****[email protected]

Henry Angulo

Verification Engineer

Austin, Texas

Verification Engineer

ASIC Design Verification Engineer

Digital Design Engineer

Engineering Development Student

ASIC Verification Engineer

ASIC Design Engineer

ASIC Customer Support Engineer

Digital Design Engineer

Southern Methodist University

Phoenix Community Junior College

Recommendations: 1

Verilog

VHDL

Processors

PCIe

Perl

Assembly Language

Unix

Linux

Justin Hohnerlein

Member Of Technical Staff

Austin, Texas

Member Of Technical Staff

Design Engineer 2

Co-op engineer

Senior Design Engineer

The University of Texas at San Antonio

University of Texas at Tyler

Lonestar College Montgomery

Recommendations: 1

Matlab

Research

Verilog

Xilinx ISE

xilinx vivado

cadance

Pspice

C++

Jeff Waller

Member of Technical Staff

Austin, Texas

Member of Technical Staff

Senior Design Engineer

Member of Technical Staff

Senior Hardware Engineer

ASIC Design

SoC Architecture

SoC micro-architect

SoC Design/Arch

The University of Texas at Arlington

Recommendations: 1

SoC

ASIC

RTL design

Low-power Design

Power Management

PCIe

PCI-X

PCI Standards

Jeff Polega

Staff Application Consultant

Austin, Texas

Staff Application Consultant

MTS ASIC Design Engineer

MTS ASIC/Layout Design Engineer

Consulting Engineer

Product Engineer

Sr. Application Engineer

Design Engineer

Intern

Carnegie Mellon University

Recommendations: 1

Software Engineering

Software Project...

Sales

Sales Engineering

EDA

ASIC

Verilog

SoC

Yunfei Wang

System engineer

Austin, Texas

System engineer

Design Engineer

CPU Design

Design Engineer

Staff Engineer

Design engineer - member of technical staff

Apps Engineer, Intern

Tsinghua University

Recommendations: 1

SoC

Low-power Design

SystemVerilog

RTL design

Static Timing Analysis

Logic Synthesis

Debugging

Functional Verification

w****[email protected]

Vishnu Jayapal

Design Engineer

Austin, Texas

Design Engineer

FPGA Design Engineer

Senior Design Engineer

FPGA Designer

University of Cincinnati

Amrita Vishwa Vidyapeetham

Recommendations: 1

FPGA

ModelSim

VLSI

Verilog

VHDL

Mixed Signal

RTL design

Xilinx

Ruofan Zhang

Senior Analog Design Engineer

Austin, Texas

Senior Analog Design Engineer

Analog Design Engineer

Analog Design Engineer Intern

Arizona State University

Huazhong University of Science and Technology

Recommendations: 0

Cadence Virtuoso

Cadence Spectre

Cadence Virtuoso Layout Editor

Matlab

Testing

Microsoft Excel

Microsoft Word

4****[email protected]

Chris Collins

Senior Vice President Product and Technology Enablement

Austin, Texas

Senior Vice President Product and Technology Enablement

Vice President Design Technology and Packaging

Engineering Manager

EDA Director

Design Engineer

Mississippi State University

Recommendations: 0

Analog

SoC

ASIC

Mixed Signal

Analog Circuit Design

Semiconductors

Engineering

c****[email protected]

Brent Macha

Analog Design Engineer

Austin, Texas

Analog Design Engineer

Systems Engineer

Electrical Engineer

Kansas State University

Recommendations: 0

Analog Circuit Design

Analog Design

CMOS

Circuit Design

Analog

Low Power Design

Electrical Engineering

Shafagh Kamkar

Graduate Research Assistant

Austin, Texas

Graduate Research Assistant

System-on-Chip Design Engineer

Graduate Teaching Assistant

Digital Design Engineer - Summer and Fall Co-op

Digital Design Engineer

Illinois Institute of Technology

KNTU

Recommendations: 0

C++

Matlab

VHDL

ModelSim

FPGA

Python

Java

Nitin Kwatra

Member Technical Staff (Software development)

Austin, Texas

Member Technical Staff (Software development)

Digital IC Design Engineer

Research Assistant

North Carolina State University

Indian Institute of Technology, Guwahati

Recommendations: 0

Digital Signal Processors

Algorithms

Verilog

n****[email protected]

Shomit Das

Graduate Intern

Austin, Texas

Graduate Intern

Research Assistant

Graduate Technical Intern

Research Intern

Software Engineer

Member Of Technical Staff

Senior Design Engineer

Postdoctoral Researcher

Teaching Assistant

University of Utah

University of Pune

Recommendations: 0

Integrated Circuit Design

Characterization

Simulations

C++

Signal Processing

ModelSim

Machine Learning

ASIC

Tanya Abaya

Circuit Design Engineer

Austin, Texas

Circuit Design Engineer

Teaching Associate

Research Assistant

Lecturer

Design-Technology Co-optimization Engineer

Analog Design Engineer

intern

Teaching Assistant

Electrical Engineer

intern

University of Utah

University of the Philippines

Recommendations: 0

Photolithography

Simulations

Matlab

Characterization

Siva Bonasu

Staff Engineer-ASIC

Austin, Texas

Staff Engineer-ASIC

Senior Design Engineer

Design Engineer

CO-OP

Digital Design Engineer

Senior Staff Engineer

Arizona State University

Jawaharlal Nehru Technological University

Recommendations: 0

ASIC

Verilog

VHDL

Digital Signal Processors

SystemVerilog

Matlab

Audio Design

Mixed Signal

i****[email protected]

Anuradha Parsi

Intern

Austin, Texas

Intern

Analog Design Engineer

Research Aide

Intern

Arizona State University

Jawaharlal Nehru Technological University

Recommendations: 0

Cadence Virtuoso

ModelSim

Verilog

Xilinx

VHDL

Matlab

SystemVerilog

Simulink

Aditi Gore

Senior Staff

Austin, Texas

Senior Staff

Logic Design Engineer

The University of Texas at Austin

Recommendations: 0

Verilog

ASIC

RTL design

VLSI

SystemVerilog

Debugging

Static Timing Analysis

Computer Architecture

Chakrapani Saralaya

RTL Design Engineer

Austin, Texas

RTL Design Engineer

Digital Design Engineer

Research Assistant

Texas A&M University-Kingsville

Recommendations: 0

Matlab

Higher Education

Research

Student Affairs

Microsoft Office

Teaching

Public Speaking

PowerPoint

c****[email protected]

Vetrivel Ayyavu

Micro-Architect / RTL Designer - Interconnect

Austin, Texas

Micro-Architect / RTL Designer - Interconnect

Director-Engineering / Engineering-Head, Hardware BU

Director-Technology (Chief Systems Architect)

ASIC Design Engineer

Enterprise SoC System Lead (Arm Neoverse Reference Design - Tech Lead)

Chip design Lead

Government College of Technology, Coimbatore

Government Polytechnic

Institution Engineers (India), Calcutta

Recommendations: 0

PCIe

Architecture

SATA

SAS

Hardware

Verilog

Telecommunications

ARM

Ruoxin Jiang

Staff Design Engineer

Austin, Texas

Staff Design Engineer

Member of Technical Staff

Design Engineer

Staff Design Engineer

Oregon State University

Fudan University

Recommendations: 0

Mixed Signal

Analog

Delta Sigma Modulator Design

High Speed A/D Design

Analog Signal Conditioning Circuit Design

Hamza Fraz

Design Engineer

Austin, Texas

Design Engineer

Applications Engineer

Principal IC Design Engineer

Research Assistant, PhD Candidate

Research Assistant

Design Engineer

Georgia Tech

Gwangju Institute of Science and Technology

National University of Science and Technology

Recommendations: 0

SystemVerilog

VHDL

Matlab

Simulations

Embedded Systems

Linux

Signal Processing

Ashraf Ahmed

Hardware Design Engineer

Austin, Texas

Hardware Design Engineer

RTL Design Engineer

RTL and Logic Design Engineer

RTL & Firmware Design Engineer

Principal Member of Technical Staff/RTL Design Engineer

University of Texas at Dallas

The University of Alabama

Recommendations: 0

SystemVerilog

Verilog

Manufacturing

FPGA

Debugging

ModelSim

Garrett Neaves

SPICE Modeling Engineer

Austin, Texas

SPICE Modeling Engineer

Engineer Training Program

Analog Consultant

Analog IC Design Engineer

Analog IC Technology Development Engineer

Analog Mixed Signal Design Engineer

Circuit Design Specialist, Intellectual Property Licensing

Analog/Mixed-Signal IC Design Engineer

Analog Mixed Signal Design Engineer

Electrical Engineer

Research and Development Engineer

The University of Texas at Austin

Recommendations: 0

Analog Circuit Design

Power Electronics Design

Integrated Circuit Design

Circuit Analysis

Worst Case Analysis

Circuit Simulation

Analog

Mixed Signal

g****[email protected]

SriHarsha Vasadi

Associate Application Engineer

Austin, Texas

Associate Application Engineer

Analog Design Engineer

Senior Design Engineer

Intern

Senior Design Engineer

Carnegie Mellon University

Indian Institute of Technology, Madras

Recommendations: 0

RF Analog Design

PLL

Analog Circuit Design

Mixed Signal

Matlab

Verilog-A

Verilog

VLSI

Rahul Ramaswami

Sr. ASIC Design Engineer

Austin, Texas

Sr. ASIC Design Engineer

Hardware Engineer

Design Verification Engineer

Design Verification Engineer - Contractor

Design Verification Intern

Test Engineer Co-op

Sr. Design Engineer

MTS Design Engineer

University of Michigan

Udacity

Recommendations: 0

Debugging

SystemVerilog

ASIC

Verilog

Hardware

Computer Architecture

Specman

Processors

David Oka

Electrical Validation Engineer

Austin, Texas

Electrical Validation Engineer

Design Engineer

VP Engineering

President/CEO

Director

Senior Project Manager

MIT

Massachusetts Institute of Technology

ABRHS

Recommendations: 0

Semiconductors

Mixed Signal

Electronics

Test Equipment

Testing

System Design

Analog

Hardware Design

Ravi Geetla

Senior Principal Analog Design Engineer

Austin, Texas

Senior Principal Analog Design Engineer

MTS Analog & Mixed-Signal Design

Senior Applications Engineer

Senior Analog Design Engineer

Arizona State University

Kakatiya University

Recommendations: 0

Mixed Signal

SoC

Analog

CMOS

Analog Circuit Design

Circuit Design

ASIC

Mack Martin

Senior Design Engineer

Austin, Texas

Senior Design Engineer

Logic Design Engineer

Logic Design Enginner

Verification and Design Engineer

Verification Engineer

Boston University

Recommendations: 0

Sherif Morcos

Component Design Engineer

Austin, Texas

Component Design Engineer

Digital Design Engineer

Carnegie Mellon University

New York University - Polytechnic School of Engineering

Recommendations: 0

Static Timing Analysis

Verilog

Computer Architecture

RTL design

Logic Design

VLSI

TCL

Perl

Pallavi Prasad

Applications Engineer

Austin, Texas

Applications Engineer

Senior Circuit Design Engineer

Summer Intern

Mixed Signal Design Intern

Member Of Technical Staff

Graduate Research Assistant at Tennenbaum Institute

Georgia Tech

National Institute of Technology Tiruchirappalli

deeksha center for learning

Recommendations: 0

Algorithms

Matlab

C++

Cadence Spectre

Cadence Virtuoso

Pspice

Allegro

Saiteja Damera

Summer Intern

Austin, Texas

Summer Intern

Graduate Teaching Assistant

Hardware Engineering Intern (Analog)

Co Op

Professional Assistant

Analog Design Engineer

Texas A&M University

Birla Institute of Technology and Science

Recommendations: 0

Matlab

Analog Circuit Design

Verilog

PSoC

NI LabVIEW

SPICE

VLSI

Daniel Acevedo

Account Planning Intern

Austin, Texas

Account Planning Intern

Sr UX Designer

UX/P Design Lead

User Experience Intern

Account Planning

English Teacher

Sr UX Designer

Senior UX Design Engineer

Sr UX Designer

Graduate Research Assistant

The University of Texas at Austin

University of Oklahoma

Booker T Washington HS Arts Magnet

Recommendations: 0

OmniGraffle

Heuristic Evaluation

Interaction Design

User Interface Design

User-centered Design

Information Architecture

Experience Design

Information Design

Joe Chien

Graduate Student Researcher

Austin, Texas

Graduate Student Researcher

Undergraduate Researcher

RF/Analog Mixed Signal IC design

Senior Member of Technical Staff (PMIC for Mobile Communication)

Senior Member of Technical Staff (RFIC Design)

Member of Technical Staff (RFIC Design)

Graduate Student Instructor

Analog Mixed Signal Design Engineer

Principal Member of Technical Staff (Cloud & Data Center Business Unit)

Staff Engineer (RF & Analog Mixed Signal IC Design)

University of California, Berkeley

University of California, Irvine

Recommendations: 0

CMOS

Mixed Signal

Analog

Simulations

Integrated Circuit...

Frederick Rush

Senior Design Engineer

Austin, Texas

Senior Design Engineer

IC Designer

Security Researcher

Staff Design Engineer

Senior Principal Engineer

Staff Design Engineer

IC Designer

Principal Engineer

Auburn University

The University of Texas at Dallas

Auburn University

Recommendations: 0

SoC

Cryptography

VLSI

Verilog

Static Timing Analysis

Place & Route

ARM

System Architecture

f*****@auburnmaple.com

Seth Herstad

Member of Technical Staff

Austin, Texas

Member of Technical Staff

Senior Staff Engineer

Senior Engineer

Design Engineer 2

Teaching Assistant in ECE department

Student Employee in Office of Student Financial Aid

Intern

Co-op with Systems Engineering Group

Co-op with Technical Assistance Center

University of Illinois at Urbana-Champaign

Recommendations: 0

SystemVerilog

Perl

Verilog

C++

Functional Verification

RTL verification

Computer Architecture

Microprocessors

f****[email protected]

Mike Babb

Lead Design Engineer

Austin, Texas

Lead Design Engineer

Design Engineer

Mixed-signal Design Engineer

Digital Design Engineer

Mississippi State University

Recommendations: 0

Mixed Signal

Integrated Circuit Design

ASIC

SystemVerilog

Primetime

RTL design

RTL

Low-power Design

Vamsi Parupalli

Teaching Assistant

Austin, Texas

Teaching Assistant

Analog IC Design Engineer

Intern

Research Assistant

University of North Carolina at Charlotte

Visvesvaraya National Institute of Technology

Recommendations: 0

Analog Circuit Design

Semiconductors

Mixed Signal

Electronics

Integrated Circuit Design

CMOS

Analog

ASIC

Tendy The

Embedded/Electronic Engineer

Austin, Texas

Embedded/Electronic Engineer

Staff Design Engineer

SMTS Prod. Dev Engineer (SoC/Logic/RTL)

Staff Design Engineer

Principal Design Engineer

Staff Design Engineer (MTS)

Senior RTL Design Engineer

University of Auckland

University of Auckland School of Engineering

Recommendations: 0

Static Timing Analysis

ASIC

VHDL

FPGA

Logic Design

RTL design

Logic Synthesis

Thomas Carlton

Engineering Scientist - QA Manager

Austin, Texas

Engineering Scientist - QA Manager

Electrical Design Engineer

Software Developer in Test II

Research Engineer

Software Developer - Test III

Software Development Engineer in Test

Software Engineer

University of South Alabama

University of Alabama

Recommendations: 0

Testing

Electrical Engineering

Troubleshooting

Software Documentation

Manufacturing

PCB design

Integration

Power Supplies

Matthew Becker

Design Engineer Intern

Austin, Texas

Design Engineer Intern

Design Verification Engineer

Graduate Assistant - Department of Electrical Engineering

Design Verification Engineer

University of Nebraska-Lincoln

Recommendations: 0

SystemVerilog

Verilog

Formal Verification

RTL design

VCS

SoC

Microprocessors

NC-Verilog

Rodolfo Uranga

Electrical Integration Intern

Austin, Texas

Electrical Integration Intern

Graduate Technical Intern

Senior Engineer

Graduate Design Engineer

Engineering Learning Center-Tutor

Electrical Systems Intern

University of Michigan

Recommendations: 0

Smita Naik

Component Design Engineer

Austin, Texas

Component Design Engineer

ASIC design engineer

The University of Texas at Austin

University of Mumbai

Recommendations: 0

SystemVerilog

Verilog

VLSI

Perl

Debugging

Semiconductors

RTL design

Functional Verification