Principal Physical Design Engineer @ Microchip Technology
Principal Physical Design Engineer @ SMSC
Physical Design Lead – DSPS @ Texas Instruments - Dallas
Accomplished IC Engineer with extensive experience in Physical Design (PD) to implement complex SoC. Proven ability to lead and make major contributions in solving PD issues. Solid experience in the area of design methodology, logic synthesis, constraint development, static timing analysis (STA), process automation. Proven success working in global diverse team environments with excellent problem solving and
Accomplished IC Engineer with extensive experience in Physical Design (PD) to implement complex SoC. Proven ability to lead and make major contributions in solving PD issues. Solid experience in the area of design methodology, logic synthesis, constraint development, static timing analysis (STA), process automation. Proven success working in global diverse team environments with excellent problem solving and team management skills, to consistently complete projects on time and with high quality results.
- Logic Synthesis.
- Constraints development.
- Static Timing Analysis (STA)
- Process automation.
- Script development.
- Design closure.
- Synopsys Design Compiler (DC/DC-Topo)
- Synopsys IC Compiler (ICC)
- Synopsys PrimeTime (PT)
- Synopsys Lynx-DS
- Magma BlastFusion (BF)
- Magma Talus
- Speak fluently in:
- Marketing SWOT/4 P’s/5 W’s analysis.
- Development of effective marketing plan.
- Marketing and business management training.
Principal Physical Design Engineer @ From January 2013 to Present (3 years) Principal Physical Design Engineer @ - Gate Array (GA) ECO flow development.
- Next generation tech node/library evaluations using ARM Cortex-M3
- Static and Dynamic power analysis. From June 2011 to Present (4 years 7 months) Austin, Texas AreaPhysical Design Lead – DSPS @ * TI Next generation multi-channel Video Decoder
* Led the physical design effort and prioritized and assigned tasks to other PD team members. Actively involved in all aspects (planning, schedule, design reviews, and etc) of physical designs.
* Interfaced with the design team and addressed critical PD issues during the RTL development phase to eliminate potential problems in backend. Drove key PD milestones, conducted the PD Red Team review with TI-Houston PD team and PD RAMP reviews.
* Mixed-signal physical integration in TI 90nm multi-VT process technology.
* Total gate count ~3M gates, total 76 memory macros, 2 on-chip PLL, and analog AFE macros.
* Performed code quality evaluation and power/performance/area (PPA) analysis.
* Responsible synthesis flow, STA constraints, backend analysis.
* Conduct PD reviews in different stages of design.
* Resource allocations and schedule alignments. From January 2007 to May 2009 (2 years 5 months) Senior IC Designer – DAV/HPA @ * TI HDTV SoC.
* Led the integration effort on analog/digital interface for both of these devices; extensively reviewed of these interfaces to ensure correct operation. In charge of physical design of several subchips that used in Analog Front End (AFE) modules
* Performed 15M gates SOC place and route using Magma BlastFusion.
* Formal verification of all modules and top-level.
* Performed STA using Synopsys PrimeTime.
* Extensive flow and scripts development that allowed us to close this design with a very small team. From January 2006 to December 2007 (2 years) Physical Design Engineer – BCG @ * PETRA - TI Titan base next generation VOIP gateway devices: 150/212MHz, 2.7 million gates, multiple subchips, complex I/O.
* Consulted design team on backend methodologies to achieve design goal effectively.
* Developed design constraints and perform logic synthesis (Design Compiler).
* Performed initial constraint clean-up.
* Pipe cleaned Pyramid/Magma design flow.
* Developed clock tree synthesis scripts, congestion analysis, and placement evaluation.
* Responsible for transferring the design to TI-Israel.
* VLYNQ2USB - Bridge device that enables broadband host controllers without a Universal Serial Bus (USB) to interface to peripherals with USB 2.0 interfaces through the VLYNQ interface.
* Developed synthesis script and constraints.
* Provided inputs to layout designer on floorplanning.
* Worked through all critical paths and perform backend ECOs.
* Developed required scripts to improve the chosen flow.
* Closed timing on all required corners (DIX) and
* SC_VLYNQ - TI communication processor serial link interface. 125MHz/145MHz, it enables VBUSP based device to communicate to another VBUSP based device through a 3-pin serial interface.
* Developed RTM (re-timing manager) timing for the IP.
* Performed DC synthesis and constraint clean-up.
* Floorplanned the subchip and developed TCL scripts for manual placement, CTS, and etc.
* Closed all required timing corners.
* Provided technical supports for all subchip (hard/soft IP) users. From February 2002 to December 2005 (3 years 11 months) Member of Technical Staff @ * Successfully demonstrated first lab prototype with Ethernet, OC-48, OC-192, TWDM and Linux.
* Responsible for architecture characterization, RTL coding, simulation, verification, and synthesis.
* High-speed logic design, verification, implementation, debugging, and modification of PRNG, Ethernet, OC-48, OC-192, and Serializer / Deserializer interfaces into FPGAs.
* Specified, implemented, simulated, and verified RTL designs using Mentor Graphics FPGA Advantage.
* Synthesis RTL design into gate level netlists using Exemplar LeonardoSpectrum.
* Used Xilinx Alliance for place-and-route and timing verification of Xilinx Vertex-E FPGAs.
* Worked together with broad-level design engineer to debug FPGA and PCB problems using Xilinx ChipScope ILA, logic analyzer, and high-speed oscilloscope. From April 2001 to February 2002 (11 months) Senior IC Designer – MSC @ * Full-functional first silicon of TI C7x MSP using TI 0.18-µm CMOS Technology.
* Designed digital CMOS circuits for mixed signal controllers using ASIC design flow and library.
* Designed and synthesized CPU core and hardware models using RTL and Design Compiler.
* Performed timing analysis using Synopsys PrimeTime STA and post route gate level simulations.
* Used timing information to modify design to improve critical paths.
* Performed instruction set evaluation.
* Pipeline implementation of defined instruction set. From April 1998 to March 2001 (3 years) Circuit Designer – MBU/DSP @ * Amazon - TI 586 microprocessor development
* Custom circuit designs and spice analysis.
* Developed repeater insertion methodology.
* Detail analysis on domino logic implementation techniques.
* Power structure and clock tree analysis for advanced microprocessor. From April 1996 to April 1998 (2 years 1 month) Product Development Engineer – PCD @ - Krypton - AMD K586 design team.
- Custom layout design on critical module (fast adder, padring, and etc.)
- LVS/DRC verifications.
- Critical path analysis on advanced microprocessor design.
- Custom datapath floorplanning. From October 1993 to April 1996 (2 years 7 months)
BS/ME, Electrical Engineering @ Utah State University From 1987 to 1993 Andrew Pua is skilled in: Physical Design
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