Senior Principal Design Engineer @ Cadence Design Systems
Verification Engineer @ Broadcom Limited
Lead Engineer @ Sasken Technologies Limited
Education:
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering @
Jawaharlal Nehru Technological University
About:
SOC Verification.
Has been mainly working on VLSI Front End.
Has experience in Specman based verification environment, Module & System level verification.
Gate Level Simulation bringup and validation.
Member of Consulting Staff (Previously Denali Software) @ From December 2013 to Present (2 years 1 month)
M.E. @ College of Engineering Pune From 2002 to 2004 B.Tech @ Jawaharlal
SOC Verification.
Has been mainly working on VLSI Front End.
Has experience in Specman based verification environment, Module & System level verification.
Gate Level Simulation bringup and validation.
Member of Consulting Staff (Previously Denali Software) @ From December 2013 to Present (2 years 1 month)
M.E. @ College of Engineering Pune From 2002 to 2004 B.Tech @ Jawaharlal Nehru Technological University From 1997 to 2001 Bachelor of Technology (B.Tech.) @ Jawaharlal Nehru Technological University From 1997 to 2001 Tenth Class @ Jawahar Navodaya Vidyalaya From 1995 to 1995 Sreenivasan Kandagatla is skilled in: Functional Verification, Specman, SoC, Memory Controller, DDR Technology, Debugging, VLSI, ASIC, Simulations, AXI-ACE, Simulation, DDR3, SystemVerilog, Gate Level Simulation, OCP
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