Yih Sheen’s Email & Phone

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Yih Sheen

Senior ASIC Design Engineer @ AmpedRFtech

Yih Sheen Contact Details

San Francisco Bay Area
Senior ASIC Design Engineer @ AmpedRFtech
Sr. ASIC design verification engineer @ QuickLogic
Design Verification Engineer (contractor) @ Microsoft

Sr. ASIC design engineer @ design block and verify it. after all design finish, run whole chip verification Design Verification Engineer (contractor) @ - Using systemverilog to create new testcases and new functions for UVM environment - Using systemverilog to write new functions/tasks to verify RTL new features in UVM environment - Run simulation to verify RTL 

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