Sr. ASIC design engineer @ design block and verify it. after all design finish, run whole chip verification Design Verification Engineer (contractor) @ - Using systemverilog to create new testcases and new functions for UVM environment - Using systemverilog to write new functions/tasks to verify RTL new features in UVM environment - Run simulation to verify RTL design and debug if test failed - Run code coverage and increase code coverage rate by writing new tests - Full Chip and Gate-level SDF verification and debug to check if test environment need to be modified. - Perform regression - Use Matlab for chip bringup validation. From July 2013 to September 2014 (1 year 3 months)

MSCE, Computer Engineering @ Northwestern Polytechnic University, MSCE From 1992 to 1994 Yih Sheen is skilled in: ASIC, SoC, Verilog, FPGA, IC, RTL design, Static Timing Analysis, SystemVerilog, VLSI, Semiconductors, Functional Verification, TCL, OVM/UVM