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Steven Nguyen

Principal Software Engineer

Principal Software Engineer at Northrop Grumman

Tempe, Arizona

Section title

Steven Nguyen's Work Experience

Northrop Grumman

Principal Software Engineer

Chandler, AZ

NXP Semiconductors

Staff Test Engineer

July 2015 to March 2019

United States

Microchip Technology

Principal Test Engineer

September 2009 to July 2015

Steven Nguyen's Education

San Jose State University

Computer engineering

San Jose State University

BS, Computer Engineering

2004 to 2007

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About Steven Nguyen's Current Company

Northrop Grumman

Frequently Asked Questions about Steven Nguyen

What company does Steven Nguyen work for?

Steven Nguyen works for Northrop Grumman

What is Steven Nguyen's role at Northrop Grumman?

Steven Nguyen is Principal Software Engineer

What is Steven Nguyen's personal email address?

Steven Nguyen's personal email addresses are s****[email protected], and e****[email protected]

What is Steven Nguyen's business email address?

Steven Nguyen's business email address is s****[email protected]

What is Steven Nguyen's Phone Number?

Steven Nguyen's phone (602) ***-*389

What industry does Steven Nguyen work in?

Steven Nguyen works in the Semiconductors industry.

About Steven Nguyen

đź“– Summary

Principal Software Engineer @ Northrop Grumman Chandler, AZStaff Test Engineer @ NXP Semiconductors From July 2015 to March 2019 (3 years 9 months) United StatesPrincipal Test Engineer @ Microchip Technology From September 2009 to July 2015 (5 years 11 months) SR TEST ENGINEER @ Texas Instruments From 2005 to 2009 (4 years) Sr. Product/ Test Engineer @ Texas Instruments Senior Product / Test EngineerParticipate in New WLAN, BT, FM IPs product (IC’s) introduction including Pre-PG activities such as test-plan documentation and Design / PE DFT weekly DFT calls.Responsible for developing new test program for characterization, qualification, Probe, and final test.Responsible for all high speed digital testing ( high speed I/0, SCAN, ACSCAN, BIST, LBIST, Memory BIST, DFT, DFM, Fault coverage) and silicon debug on ATE.Responsible for all memory tests such memory retention, memory repair test.Test HW design and ordering for test development on ATE tester platforms. Prepare for Qualification readiness and support Qualification activities. Drive new Silicon debug and product characterization to achieve 100% silicon debug and validation for release to stable manufacturing flows. Ensure successful project execution for new product introduction ramp to volume and cost and profit Attainment. test for failure analysis. From October 2005 to September 2009 (4 years) Senior Test Engineer (Mixed Signal Test Development) @ LSI Logic Corporation Working on H/W and S/W development for mixed signal and High speed testing solution.Responsible for characterization new Mixed Signal cells such as, VDACs, DACs ADCs, CODECs.Responsible for characterization new High Speed cells and IP such as, GigaBlaze, High-Speed Transceiver, High-Speed SERDES, PLL, USB1.1, USB2.0 (UTMI, UTMI+, and OTG). Development test program for Mixed-signal test chip, ASIC and Rapid Chip/structured ASIC on VLSI testers.  Development of DSP Based test routine for complex mixed signal devices for validation, characterization, production release. Working with designers to develop characterization program and effective test methodology for cores and I/Os such as LVDS, HSTL, SSTL, PECL and Mixed-signal devices. From November 1999 to October 2005 (6 years) Test Engineer II (Mixed Signal Test Development) @ Cirrus Logic Corporation Responsible for ATE test program/tool development and integration, both H/W and S/W for read channel PRML device.Development of DSP Based test routine for complex mixed signal devices for validation, characterization, production release.Work closely with Product Engineering, and package design teams to define and develop test methodologies and strategies, test tool to support tester/design features and execute the design validation debug, characterization and qualification of high frequency devices.Worked with manufacturing on wafer sort, final test yield tracking and improvement quality and design test application during silicon to bring up packages.Specific tasks include: performing product electrical characterizations using high speed / mixed-signal ATE testers (Credence LT1101, DUO, and Quartet), signal quality measurement using oscilloscopes, tester H/W and S/W validation, debug of products using logic analyzer, scopes, arbitrary waveform generator, spectrum analyzer. From June 1997 to November 1999 (2 years 6 months) Associate Validation Engineer @ Intel Corporation Responsible for the system level testing and characterization of microprocessor components failure.Responsible for technical function in support of engineering activities such as testing and debugging.Conducted engineering tests and details experimental testing to collect data or assist in research work.Performed operation test and fault isolation on system and equipment.Familiar with ATE (ITS 9000) testers and debug tool (e.g. S9K MA tool, Scope, Logic Analyzer).Worked on program development, troubleshoot test setup. From June 1996 to June 1997 (1 year 1 month)

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In a nutshell

Steven Nguyen's Personality Type

Introversion (I), Sensing (S), Thinking (T), Perceiving (P)

Average Tenure

3 year(s), 10 month(s)

Steven Nguyen's Willingness to Change Jobs



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