Prashanth Paladugu's Email Addresses & Phone Numbers

📖 Summary

R & D DV Consultant @ MICRON.com * Complete ownership of building Test Bench Architecture from the scratch.* Complete ownership of VIP Development from the scratch. * Complete ownership of Subsystem Development from the scratch.* Methodology UVM. Boise, Idaho AreaASIC UVM Verification Engineer @ Soctronics --> Created test plan for USB2.0. Achieved Functional Verification using UVM and System Verilog. --> Developed the testbench environment for USB2.0. --> Developed the test cases to verify the features such as speed negotiation, enumeration, data transfers, suspend and resume in UVM.--> Completed functional coverage and implemented RAL. From 2014 to 2015 (1 year) CaliforniaDesign Verification Consultant @ AMD --> To bring the test plan for DEBUG bus verification for STYX SOC.--> To verify the functionality of the DEBUG bus writing System Verilog assertions. --> To modify the existing test cases which are in CPP and make sure the DBUG bus works fine. --> To have understanding on UVM testcases for the debug. --> Filing the functional and document bugs in UBTS as and when required.--> Debugging the scenarios on PCIE for DEBUG bus using verdi. From 2013 to 2014 (1 year) BangaloreVLSI Trainer @ VLSI Guru Development of Memory Controller, I2C --> The Agent (driver, monitor and Sequencer) were developed using System Verilog and implemented using UVM.--> Test plan was developed and test cases were written and verified.--> The Preliminary functionality of DUT was verified by running it against itself.--> Implemented all blocks of SV UVM VE, and also complete Functional Coverage measurement including stimulus condition and device response. --> Delivered training on System Verilog and UVM methodology with labs bring up. From 2012 to 2013 (1 year) Bengaluru Area, IndiaPHY Design Verification Consultant @ LSI Corporation Protocol : EthernetIP : PCSMethodology: VMMHVL : SVDuration: November 2011 October 2012.--> Bringing up the test plan document for 100G PCS for 10 lane, and 100G 4 lane PCS, 40G PCS and 20G PCS. --> Hooking the PCS DUT with NSYS BFM and ensuring the functionality of PCS is been met. --> Identifying the bugs and filing the bugs on PCS and sometimes on the 3rd party BFM.--> Bring up the functional Coverage document for PCS 100G/40G/20G/10G and do the functional coverage for 100G PCS BASE-R for 10 and 4 lane. --> Identify the holes through Functional Coverage and bring up the new test cases and porting the existing test cases as required. --> Writing assertions as required. --> To run the regressions. From 2011 to 2012 (1 year) Bangalore Area, IndiaSr. Verification Engineer @ Soctronics Worked as Sr.Engineer for Soctronics. Protocol: MIPI. Methodology: OVM.Language: System Verilog. Responsibilities: To develop up OVC and mimic receiver phy model.Sr. Verification Consultant at AMD.SOC core verification for Krishna: Responsibilities: --> To debug signatures on CSR (Configuration space register) testing.--> Take the ownership on CNB registers and GNB registers. And debug the issues on Self test failures which includes: a) BAADDAAD. b) FUSECODE.c)DEADCODE.--> Debug using assembly language program. --> Run the regression on every new build and check the signatures. And bring the passrates to 95% before the release.--> Debugging tool used is Verdi. From 2009 to 2011 (2 years) Hyderabad Area, IndiaProduct Applications Engineer @ Xilinx To debug on Hardware designs and give comprehensive solutions for designers who are using Xilinx FPGAs Languages Used: Verilog, VHDL. Tools: Modelsim family, Synplicity. From 2006 to 2009 (3 years) PHY DV Consultant @ Qualcomm Atheros Areas of Expertise:* WIFI PHY TOP Verification. * Successful execution of test plan.* Developed scenarios as per the test plan. * Debugging scenarios on AXI and AHB bus. * Enhanced test bench at IP and Sub System Level. * Achieved 100% functional coverage. Assertion development.* Continuous Integration for IP design changes. * Ownership of RAL and Memory testplan development and verification.* System Verilog/ Verilog.* Universal Verification Methodology (UVM) From September 2016 to August 2018 (2 years) San Jose, CaliforniaUVM Applications Engineer @ Synopsys Inc Client Qualcomm • One of the focal point to the teams was resolving issues on verification related using VERDI and DVE. All issues were completed satisfactory. • Resolved over 20 complicated issues. Fixed/answered many medium to low level issues.• Filed the Change Requests on tool issues and had a track of them giving the legitimate solutions to the customer.• Continuously ran regressions with the latest VCSMX versions and qualified customer environments. Delivered the performance results to the Management. • Utilized advanced debugging via an interactive mode of debug for VERDI.• Attend to the meetings, addressing the current JIRA tickets, fixes, gather the requirements for any further training. Identify business opportunities and communicate the same to the sales team. From 2015 to 2016 (1 year) Raleigh-Durham, North Carolina Area