Harish Patel’s Email & Phone
Harish Patel
Sr Principal Design Verification Engineer @ Cadence Design Systems(Tensilica Processor)
Harish Patel Contact Details
Location:
San Francisco Bay Area
Work:
Sr Principal Design Verification Engineer @ Cadence Design Systems(Tensilica Processor)
Staff Design Verification Engineer @ Huawei Technologies
Hardware Engineer @ Cisco Systems
Education:
MSc @
University of Hertfordshire
About:
Harish Patel is skilled in: ASIC, SystemVerilog, Verilog, FPGA, SoC, Functional Verification, Embedded Systems, Debugging, VLSI, Processors, PCIe, RTL design, UVM, Hardware, Perl
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