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Pavan Sayana

Design Verification Engineer @ Synopsys Inc

Pavan Sayana Contact Details

Austin, Texas, United States
Design Verification Engineer @ Synopsys Inc
Senior verification engineer(Verification consultant @ Qualcomm) @ SmartPlay Technologies - An Aricent Company
Manager Engineering ( verification consulatant @ Samsung) @ Mirafra Technologies
No education info found.

Working on Lint ,RTL checks and System verilog Test bench checks with AMIQ DVT Simulations with Modelsim,Ncsim and VCSMX Specialties: Design Flow, Perl, Design Management(DM)

Senior verification engineer(consultant) @ From October 2010 to Present (5 years 3 months) verification engineer @ From 2007 to 2010 (3 years) trainee @ From 2009 to 2009 (less than a year)


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