Pavan Sayana’s Email & Phone

Image of Pavan Sayana

Pavan Sayana

Design Verification Engineer @ Synopsys Inc

Pavan Sayana Contact Details

Location:
Austin, Texas, United States
Work:
Design Verification Engineer @ Synopsys Inc
Senior verification engineer(Verification consultant @ Qualcomm) @ SmartPlay Technologies - An Aricent Company
Manager Engineering ( verification consulatant @ Samsung) @ Mirafra Technologies
Education:
No education info found.
About:

Working on Lint ,RTL checks and System verilog Test bench checks with AMIQ DVT Simulations with Modelsim,Ncsim and VCSMX Specialties: Design Flow, Perl, Design Management(DM)

Senior verification engineer(consultant) @ From October 2010 to Present (5 years 3 months) verification engineer @ From 2007 to 2010 (3 years) trainee @ From 2009 to 2009 (less than a year)

Mtech, 

Looking for a different Pavan Sayana?

Get an email address for anyone on LinkedIn with the ContactOut Chrome extension
Install the extension - it's free!

ContactOut is used by recruiters at 76% of the Fortune 500 companies

Similar Profiles to Pavan Sayana

Recruiters looking for Pavan Sayana also viewed
Most popular profiles
Related profiles
  • No profiles to display.

Looking for colleagues of Chris Shelby at Company Inc?

Image of Amith Amith R
Member of Technical Staff (ASIC Functional Verification)
Image of Senthilnathan Senthilnathan Duraivelu
Vice President
Image of Jonack Jonack Gupta
VP – Talent Acquisition
Image of Puneeth Puneeth R
DFT Engineer
Image of Anand Anand Mishra
Company Name Mirafra Inc
Image of Jayaprakash Jayaprakash Yangal
Director Talent Acquisition
Image of Vinayak Vinayak Angadi
Senior Design Verification Engineer
Image of Suraj Suraj Vellengar
Staff Engineer
Image of ASHRAF ASHRAF MOHAMMED
SMTS DFT Engineer