Semiconductor IC designer for over 20 years specializing in Design for Test lead roles. Architected, strategized, project managed, designed and implemented all things DFT for numerous chips for mobile phones, tablets, networking, digital TVs and FPGAs. In-depth knowledge of the whole semiconductor design process - RTL coding, verification, implementation, silicon characterisation, ATE, production and quality issues. Founded a UK based charity, Bread & Life International whose passion is in helping the less privileged around the world. Have the technical ability to grasp, modify, convey or invent DFT concepts and strategies. Also a team player who establish rapport cross functionally and across different physical locality and time zones. Able to communicate, coordinate and organise effectively and able to push through proposals with tenacity.

DFT Architect @ Design and architect next generation for DFT tools From September 2015 to Present (4 months) Eindhoven Area, NetherlandsSenior DFT Engineer @ Led and Managed DFT designs for 3 generations of modem baseband chips . Architected and specified total chip test and characterisation strategy using MBIST, IEEE 1149, IOBIST, ATPG, IP test methods. Implemented, integrated and verified Nvidia DFT technology into Icera (modem start-up acquired by Nvidia) design flow. Developed methods for ATPG compression, at-speed ATPG, debug modes for coverage improvement and test time reduction and debugging. Driven ATE chip bring-up and pattern generation and silicon issues on ATE. Coordinated DFT efforts in 3 continents and time zones – UK, US and India. Worked cross functionally with design, verification, implementation, characterisation, test and product engineering. From February 2012 to June 2015 (3 years 5 months) Bristol, United KingdomSenior DFT engineer @ Led and Managed DFT designs for 2 product lines: DTV chip and Central Office ADSL2+ Architected and specified DFT strategy from chip conception with consideration of test time, pin availability and chip complexity. Generated, integrated and verified DFT logic using EDA tools, RTL and script coding. Includes the JTAG controller, boundary scan, test pin muxing, MBIST, ATPG compression, ATPG at speed testing and analog testing. Reviewed designs and implemented coverage improvements. Generated and simulated test patterns and brought up silicon on ATE including ATPG and functional patterns Set up Teseda Tester in house, increased productivity on pattern generation and silicon debug From December 2006 to February 2012 (5 years 3 months) Bristol, United KingdomSenior Member of Technical Staff @ Managed DFT designs, test vector generation, silicon bring up, silicon testing for 2 Elixent testchips, 2 customer testchips and 1 production chip. Achieved 99.9% test coverage. Managed 65nm and SOC test strategies. Characterised in-house P&R tools with spice simulation and silicon. Integrated Hardware and software and array level debug. Set up array level transistor simulation environment. Set up automated test lab. From July 2006 to November 2006 (5 months) Bristol, United KingdomSenior Member of Technical Staff @ Same role as Panasonic. Panasonic acquired Elixent. From 2001 to July 2006 (5 years) Bristol, United KingdomSenior Design Engineer @ Business Inkjet Printer Division Prototyped printer ASIC using FPGA. Designed PCB daughter board for FGPA. From 2000 to 2000 (less than a year) SingaporeResearch Engineer @ Developed cycle accurate and analytical hardware simulation models of the printer architecture for performance analysis. Performed simulation on various architecture models. From 1999 to 1999 (less than a year) Bristol, United KingdomSenior QA Engineer @ Responsible for new products qualification in high volume manufacturing Managed flow for “Special Work Request” lots. Owned quality test programs Owned customer returns analysis and root cause analysis. From 1997 to 1999 (2 years) Senior QA Engineer @ Responsible for new products qualification in high volume manufacturing. Managed flow for "Special Work Request" lots. Owned quality test programs Owned customer returns analysis and root cause analysis. From 1996 to 1997 (1 year) Reseach Assistant @ Developed control strategies and modelling muscle stimulation Developed algorithms with assembly, C, C++ programming of microcontrollers. Researched and developed electrical stimulator for controlling paralysed muscles. Scientific reporting, grant applications, and medical equipment qualification. From 1993 to 1996 (3 years) FA Engineer @ In-depth failure analysis on 80486 processors using e-beam, SEM, EM, liquid crystal and IMS testers. Setup database of failure signatures. From January 1992 to December 1992 (1 year) Penang, Malaysia

Master of Engineering, Biomedical Engineering @ National University of Singapore From 1993 to 1996 Bachelor’s Degree, Computer systems and electrical Engineering, First Class Honours @ Monash University From 1988 to 1991 Hui Lau is skilled in: DFT, Silicon, ATPG, RTL design, Analog, ASIC, SoC, BIST, IC, Testing, JTAG, Debugging, Verilog, Functional Verification, EDA, RTL Design, Perl, Semiconductors, Embedded Systems