Vinod Bhat's Email Addresses & Phone Numbers

Member of Technical Staff @ Ambarella From October 2010 to February 2011 (5 months) Senior IC Design Manager @ InvenSense, Inc. Lead digital architect for motion DSP design and lead designer for multiple digital IPs From June 2013 to November 2014 (1 year 6 months) IC Design Manager @ InvenSense, Inc. Architecture of sensor chip with DSP...

Member of Technical Staff @ Ambarella From October 2010 to February 2011 (5 months) Senior IC Design Manager @ InvenSense, Inc. Lead digital architect for motion DSP design and lead designer for multiple digital IPs From June 2013 to November 2014 (1 year 6 months) IC Design Manager @ InvenSense, Inc. Architecture of sensor chip with DSP for 3 axis gyroscope, 3 axis accelerometer and barometerRTL design of motion processor, power sequencer, FIFO, register map and SPI/I2C serial interfaces From June 2012 to June 2013 (1 year 1 month) Senior ASIC Design Engineer @ NVIDIA Implementation of a tuneable ring oscillator for a closed loop DVFS circuit.Rewrote module that parses inputs from multiple streams and either uploads this data to memory or reformats for consumption further upstream of camera sensor interfaceAdded logic to do stuck-at-pixel/outlier removal of data from camera sensor From February 2011 to June 2012 (1 year 5 months) Senior ASIC Design Engineer @ NVIDIA Developed algorithm for notebook CPU-GPU power sharingArchitected and implemented key improvements in CPU-DDR3 data path RTLDeveloped algorithms to optimize power consumption of mobile chipset in all ACPI sleep statesDesigned and implemented RTL for Azalia audio controller Designed and implemented extensive TCP packet processing in RTLDesigned and implemented TCP segmentation and TCP/IP checksum generation in RTL From June 2002 to October 2010 (8 years 5 months) SoC Platform Architecture Program Manager @ Apple Cupertino, California, United StatesEngineering Manager, Artificial Intelligence Product Group @ Intel Corporation Roadmap planning, schedule planning and front end silicon execution for Crest family of SOCs for deep learning training and inference acceleration.• Managed team of up to 35 on site and remote design and verification engineers. Delivered microarchitecture, RTL design and design verification.• Coordinated with Algorithms, Architecture, Software and Marketing teams to define product requirements and architecture.• Provided architectural and microarchitectural reviews and analyses. From April 2017 to June 2020 (3 years 3 months) San Francisco Bay AreaDirector, IC Design @ InvenSense, Inc. Architecture and front end silicon execution for MEMS motion sensor and MEMS fingerprint sensor SOCs.• Managed on site and remote design engineers tasked with microarchitecture, RTL design, synthesis and timing closure.• Coordinated with Mixed signal, Software and Marketing teams to define Product requirements and architecture spec.• Lead digital architect for Dual Core SOC design for fingerprint sensor.• Program lead for 6 axis OIS/EIS (Optical/Electrical Image stabilization) plus motion From November 2014 to April 2017 (2 years 6 months)