ASIC/FPGA Developemnt, Co-Founder @ Taped out Cloudvue RemteFX decoder with Faraday using UMC foundary. Designed internal DWT engine, 2D engine, up and down scalar, and display controller, and various Win 8 RDP engines. Integrated external PCIE, DDR2, DDR3, and USB, Video Decoder for next generation ASIC. Prototyped various hardware designs using Xilinx Virtex7 and Virtex5 FPGAs. From October 2010 to Present (5 years 3 months) Principal Hardware Developer @ Taped out Microsoft RemoteFX technologies in eASIC Nextreme uses a combining of LUT cells with customized single-via interconnect. Ported C models for verifying coded Verilog RTL of MPPC RDP protocol. From January 2008 to September 2010 (2 years 9 months) Senior Member of Technical Staff @ Prototyped various hardware modules using Virtex5 and Spartan3 FPGA which including synthesis and P&R. Designed wavelet codec engine, cross-bar fabric, memory and display controller in Verilog. From May 2006 to December 2007 (1 year 8 months) Senior Staff Design Engineer @ Designed DDR controller, DMA controller, and bus unit with AMBA 2.0 interface. Integrated external IPs for SDIO and NDFLASH, TV encoder, MIP, and USB for SOC in cell phone media processor. From April 2005 to April 2006 (1 year 1 month) Sr. Design Engineer @ Implemented and verified CAVLC and CABAC variable length decoder for H.264 video decoder. Designed and verified fractional up and down scalar between QCIF and D1 resolution. From November 2003 to April 2005 (1 year 6 months) Design Manager @ Handled backend tape out process for flat panel scalar chip. Used Physical Synthesis and Prime Time for timing closure. Stitched scan chains by DFT compiler and generated vectors by Tetramax. From June 2002 to November 2003 (1 year 6 months) Member of Technical Staff @ Designed Egress Storage ASIC and verified Local Buffer Manager ASIC for Line Card. From June 1999 to May 2002 (3 years) Member of Technical Staff @ Designed 3D graphic engine, MPEG2 decoder, and various blocks inside a family of graphic chips. From April 1993 to June 1999 (6 years 3 months) System Validation Engineer @ Designed verification boards to debug i586 and i486 and coded dis-assembler for i386 for testing. From February 1988 to June 1993 (5 years 5 months) Co-op Engineer @ Created simulation model for Apple Link which interfaced between Macintosh and Micro-Vax. From January 1987 to June 1987 (6 months)

Master of Science (M.S.), Electrical and Electronics Engineering @ San Jose State University From 1986 to 1988 Bachelor of Science, Electrical and Electronics Engineering @ California Polytechnic State University-San Luis Obispo From 1981 to 1985 Thomas Young is skilled in: Verilog, ASIC, FPGA, SoC, Debugging, Xilinx, PCIe, IC, USB, Logic Synthesis, Primetime, Timing Closure, PCB design, Simulations, Hardware