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Stephan Bourduas

System Engineer @ Intel Corporation

Stephan Bourduas Contact Details

Greater Boston Area
System Engineer @ Intel Corporation
Design Verification Engineer @ Cavium Inc
Component Design Engineer @ Intel Corporation
M.A.Sc. @ Concordia University

I am a design verification engineer with experience using UVM, SystemVerilog and SystemC/C++ to perform coverage driven validation of complex microprocessor designs. I have developed reference models using SystemC/TLM and developed stimulus libraries that were used to generate constrained random stimulus to fill coverage. Specialties: Software engineering, high-level modeling, SystemVerillog, VHDL, C++, TLM, UVM, OVM, Java, Perl, 

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