I am an electrical engineer with 20+ years experience in designing and verifying SoC ASIC and FPGA devices including Xilinx, Altera, Actel and Lattice. RTL Languages I use are VHDL, Verilog and SystemVerilog Other languages are C / C++ and SystemC. Also used DO-254 and perform Lab debug using Logic Analyzers and Oscilloscopes. Use IBM Telelogic DOORS 9.2 DoD Secret Clearance Specialties: - Languages: C/C++, UVM 1.1C, SystemVerilog,Verilog,VHDL,Matlab,,VERA, SystemC,TCL - Simulators: Synopsys VCS,Cadence Verilog NC Sim,Modelsim,Aldec Active-HDL, ISE ISIM - EDA Tools: Synopsys Design Compiler,Primetime,Synplicity,Xilinx ISE Foundation, Chipscope - O/S's: Unix,Linux,SunOS,AIX,Windows XP - Devices: Xilinx, Altera, Actel,Lattice,Toshiba,TSMC, NEC, Synopsys HAPS-51 - Protocols: PCI Express, Ethernet,SCSI,PCI,SONET,AGP,OC192, AMBA - Revision Control: RCS, SCCS, CVS, Atria Clearcase

Consultant @ Simulated ASIC using Aldec Reviera Pro 2013.2 using SystemVerilog and UVM 1.1C. Also participated in Boston and San Jose Synopsys Users Group on Technical committee. From January 2002 to Present (14 years) Greater Boston AreaElectrical Engineer Contractor @ Design verification of 25Gb Ethernet IP 803.2by: - development of verification components and test cases in UVM 1.1C/System Verilog environment - debugging of test cases using Cadence simulator NCSIM, Simvision and Verdi Debug system - running RTL regressions using Linux-based compute farms - used Cadence IEV formal verification tool and PSL. From June 2015 to September 2015 (4 months) Engineering Consultant @ Simulated Xilinx Spartan 6 FPGA used in WAAS GPS system for FAA to DO-254 certification level B. Used Modelsim PE 10.0 and Verilog in Xilinx ISE foundation 14.3. Help write, review and validated requirements and specifications for such documents as PHAC, HVVP, etc. From November 2012 to September 2014 (1 year 11 months) Greater Boston AreaElectrical Engineer (contract) @ Designed and verified FPGA using Xilinx, ISE foundation 14.1 From May 2012 to August 2012 (4 months) Electrical Engineer Contractor @ Performing FPGA verification with Systemverilog, Modelsim 10.0, used in Medical equipment. From 2011 to 2012 (1 year) Consultant @ Assisted in design and verification of Xilinx Virtex V FPGA using VHDL, Xilinx ISE Foundation 12.3, VHDL for a Medical System. From 2011 to 2011 (less than a year) Verification and Validation FPGA Contractor @ Verifying Altera Cyclone III FPGA design, which used ARINC-429 and ARINC-717 aviation communication protocols, using Quartus II and Aldec-Active HDL 8.2 digital logic simulator, SystemVerilog and IBM Telelogic DOORS 9.2. Contributed to documents such as CEH, PHAC, HAS, HVP, HVVP, HDP,CEHR and HCMP for do-254, level A. Provided Validation of design requirements using Verification Testbench. From August 2009 to August 2010 (1 year 1 month) Consultant @ Assisted in design and verified verilog / VHDL in dual Xilinx Virtex-5 SX90T FPGA’s on VME/64 I/O processor board, A/D, Gigabit Fiber, Rocket I/O, using Modelsim 6.2, Xilinx ISE Foundation 10,1, Orcad, Xilinx Coregen for use in Radar systems. From October 2008 to April 2009 (7 months) Contractor @ Participated in design, verification and lab debug of high speed DSP processing of JCREW radio signals using Xilinx Vertex5 LX330 FPGA, verilog, Synplicity HAPS-51 prototype board, Matlab and PCIe. Used ISE foundation 10.1, PCIe, .net 2005, C/C++, DLL. From March 2008 to September 2008 (7 months) Consultant @ verified PCI interface to 8 Core ARC multiprocessor ASIC using Verilog and creating PCI transactor. From October 2007 to December 2007 (3 months) Consultant @ Verified Actel APA1000 FPGA used on A380 Motorcontroller using VHDL, Modelsim, FPGA Advantage and Synplicity. Followed DO-254 / D0-254 standards - Level A Certification. Verified Xilinx Vertex II Pro FPGA using VHDL, Verilog, TCL,Modelsim for Image Processing Board in aircraft. From August 2006 to July 2007 (1 year) Consultant @ verified microcontroller for Automotive industry that used dual PowerPC microprocessors using verilog. From May 2006 to August 2006 (4 months) Electrical Engineer (Contractor) @ Verified Actel FPGA used in an avionics electronics. From January 2005 to August 2005 (8 months) Electrical Engineer (Contractor) @ • Created test vectors for verilog model of DSL modem with PCI, USB and SCI interface using ModelSim. Prepared verilog netlist of Xilinx Vertex 2000 FPGA. Used Linux shell environment for simulation platform. From August 2001 to October 2001 (3 months) Electrical Engineer (Contractor) @ • Created verification tests for 12 million gate Graphics Processor ASIC using Verilog, VHDL and Visual C++. From August 2000 to July 2001 (1 year) Electrical Engineer (Contractor) @ • Created and simulated Verilog board model of OC192 10 Gigabit Sonnet / Ethernet line card including 5 million gate array IBM 0.18 um ASIC on ASIC-Alliance TestbenchPlus environment, C and PLI, Motorola MPC801 Processor. From November 1999 to July 2000 (9 months) Vice-chair @ I organized and supported the chair in running the volunteer meetings as well as the lecture series. I also took care of mailings, directory printings and membership renewals. From January 1995 to December 1999 (5 years) Electrical Engineer (Contractor) @ Verified a PCI to Ethernet ASIC using Verilog. From 1997 to 1999 (2 years) Electrical Engineer (Contractor) @ • Wrote and implemented verification test plan to verify verilog models of I/O adaptor cards for Chip Express ASIC that interfaced 68030 processor to Serial Communications Controller. From January 1998 to December 1998 (1 year) Electrical Engineer (Contractor) @ • Wrote and implemented verification test plan to test out NEC 250,000 gate ASIC that arbitrated among 15 ports in 50 gigabit ATM router using Cadence VerilogXL, Chronologic VCS, Signalscan on Ultrasparc workstation. From January 1997 to December 1997 (1 year) Consultant @ Simulated and verified in Verilog DSP ASIC for mini-cell cellular system. From November 1995 to July 1996 (9 months) Electrical Engineer (Contractor) @ • Created and simulated Ethernet, Token-ring bridge board models using Mentor 8.2 Quicksim, Actel FPGA, TI ASIC, LMC, 68302 and 80960 processors, AMD 7990 LAN chip and LM1000 hardware modeler. • Programmed in AMPLE and LMC PCL code for 80960 processor. From January 1993 to December 1994 (2 years) Electrical Engineer (Contractor) @ • Gigabit SONET fiber optic WAN/LAN project. • Created and simulated Gigabit SONET fiber optic LAN board model. Used Valid (Cadence), Synopsys, VHDL on AIX IBM RS6000 system. Participated in LAN board lab debug. From January 1992 to October 1992 (10 months) Electrical Engineer (Contractor) @ • Simulated 150,000 date array, 1.0 micron CMOS, 208 pin flat pack. Gate array interfaces to C710 SCSI I/O processor to Microchannel bus. Gate array was successfully debug and working in 2 weeks in lab. From January 1991 to August 1991 (8 months) Electrical Engineer @ • Designed, schematic captured, simulated and debugged Toshiba 3200 gate array, 1.5 micron 68 pin grid for Vaxcluster CI Switch. Received patent #4,897,833 for array that arbitrates 8 nodes. Used CAE2000 schematic capture system. Simulated using DECSIM. Timing verified using AUTODLY. Achieved fault coverage of 97%. Designed NTSC/PAL decoder board for interactive video information system. Investigated other video technologies for multimedia IVIS. From January 1984 to October 1990 (6 years 10 months)

MS, Computer Science @ Boston University From 1992 to 1999 BS, Electrical Engineering @ Syracuse University From 1975 to 1979 Ronald Goodstein is skilled in: UVM, FPGA, Verilog, ASIC, SystemVerilog, VHDL, Embedded Systems, EDA, DO-254, Hardware Architecture, Simulations, SoC, Digital Electronics, TCL, Debugging