I am Rinachi Garg, Senior Engineer with Chipset Architecture Team at Qualcomm. I have 4 years of work experience at Qualcomm and at my previous company Larsen & Toubro Ltd. In my current role at Qualcomm, I am working with Platform Chipset Architecture Team with the following responsibilities: • Lead Engineer for performance analysis and modelling Inter-Chip connectivity interface • Drive Architectural Interface decisions for optimization, design and IP areas with various stakeholders and teams • Analyzing Chipset Partitioning options for Modem, RF, Power Management ICs and Memory for Optimization & Cost • Collaborate with various teams to analyze die area, packaging, eBOM, PCB area, bumps and balls, GPIOs, supplies and regulators, power grid, technology node, interfaces and features I have prior experience and interest in Computer Vision, Image Processing and Robotics. I have worked on various projects at school and during previous internships. I am proficient with MS Office, Python, MATLAB, SIMULINK, C, C++, SysML, System C, Raphsody, Eclipse, Assembly, Verilog and Arduino I am passionate for professional and personal growth of women and encouraging girls in STEM fields. I am board member and active leader in voluntary organization Qualcomm Women in Science and Engineering.

Senior Engineer, QCT Chipset Architecture @ • Lead Engineer for performance analysis of Inter-Chip connectivity interface • Drove Architectural Interface decisions for optimization, design and IP areas with various stakeholders • Experience with Modem Chipset Architecture and Analyzing Chipset Partitioning options for Baseband, RF, Power Management ICs and Memory for Optimization & Cost • Collaborated with various teams to analyze die area, packaging, eBOM, PCB area, bumps and balls, GPIOs, supplies and regulators, power grid, technology node, interfaces and features From March 2015 to Present (8 months) San Diego, CAEngineer, QCT Chipset Architecture @ • Developed Performance Analysis Model for Inter-Chip connectivity interface using SysML and C++ in Raphsody and Eclipse • Designed I/O data format using Excel & Python scripts to pre & post process Data to & from model • Performed Simulations for various use-cases & Recommended Architecture Parameters based on performance • Designed Algorithms and Developed end-to-end performance model for PCIe through-put analysis using MATLAB/SIMULINK • Simulated performance using model and correlated results with Chip Hardware using PCIe link • Analyzed and Recommended parameters for various Hardware and Software knobs in the system • Supported Platform Chipset Architecture for Snapdragon Processors and Modem by documenting Architecture specifications, analyzed eBOM and PCB area From February 2013 to February 2015 (2 years 1 month) San DiegoEngineering Intern, QCT Chipset Architecture @ • Designed, tested and deployed custom automation framework for exhaustive chipset partitioning and architecture analysis using MATLAB & Excel for analyzing I/O pins, bumps and area for chipset partitions • Team Lead for Project ‘QVision for the Blind’ selected in Top 10 entries for Intern innovation competition. Secured 2nd place in the contest and had an opportunity to meet & pitch the idea to former CEO From May 2012 to August 2012 (4 months) San Diego, CA, USAGraduate Engineer, Switchgear Design and Development Center, R&D @ • Worked at R&D of Switchgears with Life Cycle Management Team and responsible for value engineering projects, product improvements and competitive analysis • Engineered, Proposed and Tested a design change in Under Voltage Release for Molded Case Circuit Breaker • Proposed design changes for MCCBs to reduce Material and Manufacturing Cost From August 2010 to July 2011 (1 year) Mumbai, IndiaIntern, Indian Institute of Remote Sensing @ Research Intern at Photogrammetry and Remote Sensing Division. • Analyzed the changes in Indian terrain using remotely sensed images in ENVI using Image Processing by implementing the code for Change Vector Analysis Algorithm in Interactive Data Language (IDL) on LANSAT images. • Analyzed land cover by implementing the code for fuzzy logic classification of LANDSAT images From June 2009 to July 2009 (2 months) Dehradun, IndiaIntern @ Worked at Rapid Prototyping Lab at mechanical Engineering Department to develop the algorithm and code in MATLAB to manufacture the rapid prototype using Selective Laser Sintering Machine which helped in the study of surface roughness of the prototypes manufactured using Image Processing Algorithm From June 2008 to July 2008 (2 months) Delhi, India

Master's degree, Electrical Engineering- Systems @ University of Michigan From 2011 to 2012 Bachelor's degree, Electrical Engineering @ Delhi College of Engineering From 2006 to 2010 Rinachi Garg is skilled in: Chipset Architecture, Matlab, Verilog, Simulink, Digital Signal..., Signal Processing, Python, Computer Architecture, Image Processing, C, Computer Vision, Simulations, Algorithms, C++, SysML, Interconnects, Mobile Interfaces, High Speed Interfaces, PCIe, Throughput Modeling, Simulation Tools, Modeling Tools, GUI, Scripting, Inter-chip Communication, Chipset Performance, Embedded Systems, FPGA, Engineering