Ramesh Madhira's Email & Phone Number

Design Engineer - Contractor at asic North at ASIC North

Cache Coherency | Out Of Order CPU | PCIE Ordering | ASIC Design Verification | Cadence Palladium | ARM Architecture at NVIDIA

Server + FPGA Design Engineer at Intel at Qualcomm

Verification Consultant at Cadence Design Systems

Senior Staff Engineer at Samsung Electronics at Samsung Electronics

Senior Vice President of Engineering at Axiado at Axiado Corporation

Circuit Design and Methodology Engineer at Qualcomm

Verification Eng for ARM Server and Mobile Sub-Systems & SOC chips at Qualcomm at Qualcomm

Senior Hardware Design Engineer at Microsoft at Qualcomm

Principal Engineer at Qualcomm, Inc at IBM

Solutions Engineer at Cadence Design Systems at Cadence Design Systems

Micello, Inc.