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Rajesh Rajaram

Sr. Project Associate

SOC Design Engineer at Intel Corporation

San Francisco Bay Area

Section title

Rajesh Rajaram's Email Addresses & Phone Numbers

Rajesh Rajaram's Work Experience

IC&SR IIT Madras

Sr. Project Associate

March 1995 to September 1997

Wipro Technologies

Sr. VLSI Technical Consultant

1999 to June 2016

Intel Corporation

SOC Design Engineer

Sacramento, California Area

Rajesh Rajaram's Education

Indian Institute of Technology, Madras

MS, Microelectronics, 8.4/10

1996 to 1999

Government Engineering College Aurangabad

BE (EC), Electronics and Telecommunications

maulana azad college

HSC, electronics physics

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56% Left Brained
44% Right Brained

Rajesh Rajaram's Estimated Salary Range

About Rajesh Rajaram's Current Company

IC&SR IIT Madras

Frequently Asked Questions about Rajesh Rajaram

What company does Rajesh Rajaram work for?

Rajesh Rajaram works for IC&SR IIT Madras

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Rajesh Rajaram is Sr. Project Associate

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Rajesh Rajaram works in the Semiconductors industry.

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Rajesh Rajaram's colleagues are Yong Wu, Jie Sun, Jackson He, Bin Wu, Xue WANG, Dan Zhang, Lei Wu, Ted Ye, Brent Young, and Yunfa Li

About Rajesh Rajaram

📖 Summary

Sr. Project Associate @ IC&SR IIT Madras From March 1995 to September 1997 (2 years 7 months) Sr. VLSI Technical Consultant @ Wipro Technologies * System Architecture experience in developing architecture for product from specification. Proposed and developed ASIC SoC and FPGA based solutions.* Developed Architecture solution for an Extreme performance H.264 real time QVGA Encoder system for a leading Japanese broadcaster to broadcast TV channels to mobile devices. * Part of several successful tape-outs in various responsibilities such as Synthesis+DFT, JTAG + MBIST insertion, LEC, pre and Post-Layout sign-off STA, timing and logical ECO's in various process technology nodes starting from 90nm, 65nm, 40nm, 22nm to most recent 14nm for various gate counts starting from 3M to 55M. * Vastly Experienced in IP development. + Involved as technical lead for Development of a full featured RapidIO Gen-2.2 IP core supporting x1, x2 and x4 lane modes, each lane capable of operating at 6.25GBaud. + Development of MIPI specified DSI and CSI PHY IP's which includes development of DFE and integration of AFE. + Developed multiple ARM AMBA AHB based Primecell IP including multiple flavors of complex Memory controllers and DMA controller.* Image and Video processing domain solutions such as Pro-MPEG based system, display controllers, JPEG2000 IP.* Mixed signal digital PHY block development. + For MoCA ASIC, Micro-architect and design critical blocks such as DC-Offset Estimation and Correction, I-Q Calibration and Correction, Numerically Controlled Oscillator based Tone Generator with amplitude control, Gain Extraction and Control for LNA, PA, LPF, Mixer, Squarer etc. + For MIPI IP's, design and development of resistor compensation block, * Strong experience in performing top level and sub-system level RTL integration. + Ownership of 1.8Million gate sub-system consisting of 800MHz/1600MHz DDR3 Controller IP + PHY Hard Macro sub-system. Design of additional features such as design of Overlapped Data protection for DDR3 data bus and address protection schemes. From 1999 to June 2016 (17 years) SOC Design Engineer @ Intel Corporation Multiple IP Integration into SoC's, and Validation , Formal flows. Sacramento, California Area

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In a nutshell

Rajesh Rajaram's Personality Type

Introversion (I), Intuition (N), Thinking (T), Judging (J)

Average Tenure

9 year(s), 9 month(s)

Rajesh Rajaram's Willingness to Change Jobs



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