ASIC Design & Verification

Engineer Senior @ • Verified and validated for four tapeouts and three bringups. • Designed microarchitecture and coded RTL logic for direct memory accesses management in next-generation chip • Assisted in time-critical gate-level simulations, timing violations debugging, and board validation tests for tapeout and bringup, respectively • Performed both top- and block-level simulations and verification • Authored block-level regression testbenches to validate access to flash and top-level tests From December 2012 to Present (3 years 1 month) Engineer @ • Devised and validated tests for several critical features including zero-copy networking, message signaled interrupts, vital product data, and EEPROM • Developed PCI-E utility and GUI to access registers for ASIC bringup and FPGA verification, deployed company-wide • Tested I/O Virtualization traffic between ASICs From December 2011 to December 2012 (1 year 1 month) Engineering Intern @ • Authored automation scripts, accelerating speed of RTL verification procedures leading to detection of unknown bugs • Executed and automated top-level chip simulations, eliminating need for physical monitoring • Designed critical testcases From March 2011 to December 2011 (10 months) Hardware Engineer @ • Created verification utility to detect, display, and guide the elimination of synchronization errors between clock domains • Designed regression test circuit to ensure a successful synthesis environment for every tool and chip update • Developed tool for generating optimal area/power/timing memories for RTL designers From July 2008 to September 2009 (1 year 3 months) Hardware Engineer College Intern @ • Performed physical design on a block of the Cisco Packet Processor from RTL Synthesis to Timing Analysis • Enhanced Timing Analysis flow by improving processor timing report management From May 2007 to August 2007 (4 months) Business and Software Assistant @ • Managed online business and conducted in-store sales • Tested computer parts, designed and published advertisements, and created web pages From June 2005 to August 2005 (3 months)

B.S., Electrical Engineering @ Purdue University From 2004 to 2008 Master’s Degree, Electrical Engineering @ San Jose State University From 2012 to 2015 Electrical Engineering @ Santa Clara University From 2009 to 2009 Computer Science @ San Jose State University From 2010 to 2011 High School, 4.0 / 4.0 (Class Honors) @ Brebeuf Jesuit Preparatory School Pranav Kachhwaha is skilled in: Verilog, ASIC, Perl, EDA, Cadence, TCL, SoC, C, RTL design, System Verilog, PCIe, Functional Verification, Tapeout, Bring-up, FPGA