Pranav Kachhwaha’s Email & Phone

Pranav Kachhwaha Contact Details

San Francisco Bay Area
Engineer Senior @ Emulex
Engineer @ Emulex
Engineering Intern @ Emulex
Master’s Degree, Electrical Engineering @ San Jose State University

ASIC Design & Verification

Engineer Senior @ • Verified and validated for four tapeouts and three bringups. • Designed microarchitecture and coded RTL logic for direct memory accesses management in next-generation chip • Assisted in time-critical gate-level simulations, timing violations debugging, and board validation tests for tapeout and bringup, respectively • Performed both top- and block-level simulations and 

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