Pat Hann’s Email & Phone

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Pat Hann

Design Verification Engineer @ Samsung Austin R&D Center

Pat Hann Contact Details

Austin, Texas Area
Design Verification Engineer @ Samsung Austin R&D Center
Technical Leader @ Cisco Systems
Hardware Engineer @ NetSpeed
@ Florida Institute of Technology

Lead Design Verification Engineer Testbench Architecture and Methodology Project planning, scheduling, and managing resources FullChip and Unit Level verification Test plan development and execution with functional and code coverage metrics Languages: System Verilog, Verilog, Vera, SVA, Perl, C/C++ Methodologies: UVM, VMM, RVM ARM Architecture, AMBA, AXI, ACE Multiprocessor Memory Subsystem, Level2 Cache, Cache coherency verification Cisco Catalyst 

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