I am seeking an engineering or management position with a technology company that will allow me to apply my broad engineering, business, and management experience to create exciting products and business solutions. As a computer engineer I enjoy working with both hardware and software as well as full systems and can contribute at a very high level to almost any organization. I am eager to apply my creative energy, extreme dedication, and work ethic towards the success of the company in this fast growing high-tech field. • • Over 15 years in Electronics, Silicon, and Software engineering and management • Deep knowledge in Altera FPGA design and IP experience including board, chip, and tools • Recent new silicon ARM CPU bringup experience including chip, peripheral, PCB debug • Excellent communications and team lead experience including planning, design, and rollout managing teams in the US and Asia on a daily basis • Extensive new silicon bring up and debugging skills in a lab environment using real-time and sampling oscilloscopes, logic analyzers, spectrum analyzers, power supplies and loads, as well as production support, soldering, digital and analog debugging • Excellent high-speed IO design experience to 28 Gbps including signal integrity simulation • Hardware skills including schematic, PCB, Verilog and VHDL logic and IP design, external memory, software, CPU, and systems design • Software skills including embedded C/C++ design, software systems, firmware, networks • Windows and UNIX/Linux systems setup, networking, management and support

Member of Technical Staff @ Product Engineering department working on system level verification and SoC device test and bringup. From June 2014 to Present (1 year 7 months) Manager High Speed IO Group @ •• Drove creation of the new Qsys Test System (QTS) next generation FPGA example design suite for FPGA development kits to shows transceivers (XCVR) up to 28 Gbps, LVDS up to 1700 Mbps, and external memory using DDR3, QDRII, RLDRAMII to 1866 Mbps • Architected a new PCIe to DDR3 design suite documented in AN431 by Altera using programmable mSGDMA engines and Jungo PCIe drivers for Windows • Joined VITA to represent Altera in FPGA Mezzanine Card (FMC) specification development and steering committee. Drove creation of new Altera version to increase transceiver counts • Drove creation of Perl-based FPGA example design regression test system to code-update, generate, compile, check timing, and verify hardware performance under new builds of Altera’s Quartus II FPGA compiling tool for over 300 chip designs and 30+ hardware target packages • Drove creation of a new Power Monitor and Clock Control applications to allow in-system control and status of real-time FPGA power and clock frequency including both CPLD VHDL and Verilog and PC-based C and Java-based Application code and Netbeans GUI • Hired and trained team in China and Malaysia to augment design team in California • Created the Board Test System IP to control and verify Altera IP for both external memory interfaces (EMIF) and transceivers (XCVR) including FPGA VHDL and Verilog, NIOS II CPU C-based firmware, and PC-based C and Java-based Application code and Netbeans GUI • Invented High-Speed Mezzanine Card (HSMC) interface specification linking programmable FPGA-based hardware to fixed function daughter cards in 2006 used by dozens of companies to develop daughter cards for networking, DSP, video, and memory applications with ASSP's • Promoted to manager with a staff responsible for high-speed board design, signal integrity analysis, FPGA and CPLD design, software design for embedded processors, application and GUI design for Windows and Linux, and documentation and support of these products. From 2006 to December 2013 (7 years) Member Technical Staff @ • Design lead for Stratix Memory Board II and Stratix II Memory Board II to demonstrate QDRII at 400Mb/s to 600Mb/s as well as DDR2 Devices and DIMM from 200Mb/s to 667Mb/s. Worked with IP engineers as no IP was yet developed for these memories • Design lead for Stratix PCI and Stratix PCI Pro Development Kits. Single-chip design has 64-bit PCI/PCI-X bus up to 133MHz, a single DDR SODIMM operated up to 200MHz, and two source-synchronous LVDS busses at 1Gbps with interoperability with a BroadCom BCM1250 network processor and a HyperTransport Consortium standard backplane. • Design lead for Stratix Rapid IO / HyperTransport Demo Board developed ahead of silicon and software availability. Developed test for two 800Mb/s 8-bit LVDS ports and successfully demonstrated on first article PCB across a Tundra RIO backplane directly and a Broadcom HT backplane through micro-coax ribbon cables. Received award for effort. • Moved to Component Applications High-Speed I/O Group in 2003. • First to demonstrate configuration of an Altera FPGA over the internet using a web-browser on a PC accessing pages from web-server running in the FPGA using on 32K of code including TCP/IP stack and server. Used to secure $40M design win at major Cellular OEM in Korea. Received award for effort. • Set up office’s software lab including PCs and UNIX Workstations for running Quartus II on Solaris, HP/UX, Silicon Graphics, Linux, Windows NT, Windows 2000, Windows 98 • Led customer support team for Southwest Region before moving into embedded specialist role specializing in NIOS II soft-core CPU and embedded tools support including hardware acceleration, TCP/IP networking and MAC core, as well as flash routines and multi-core • First employee hired for Altera San Diego engineering office. Involved in setting up all equipment and hiring employees within applications engineering, the largest team in the office. From 2000 to 2006 (6 years) Systems Engineer @ • VisiCom was sold to Titan Corporation (later bought by L3 communications). • Designed an Intel i960 RISC-based I/O controller card that contains two 64-bit PMC slots for physical-layer I/O cards as well as on-board serial, 10/100 Ethernet, and a 64-bit VME Master interface. 100MHz SDRAM SODIMM ran on first PCB revision. Helped port VxWorks BSP to run on the board to emulate Navy NTDS ship communications IO software From June 1999 to November 2000 (1 year 6 months) Systems Engineer @ • Responsible for design and implementation of many VHDL programmable logic designs done in PAL, CPLD, and FPGA from Xilinx, QuickLogic, and Actel. • Designed the MMI-430 Quad Audio Board based on 4 Motorola DSP56000 processors with both private SRAM and shared DRAM. Designed DSP bus switch and interface to SDRAM and VME64 with VHDL logic design in Xilinx XC4000 FPGA. • Designed the TAS UniModule, a single FPGA-based reprogrammable form-fit circuit card that could replace up to 64 individual function circuit cards into a single XC4000 FPGA for a ship-based radar From October 1995 to June 1999 (3 years 9 months)

Bachelor of Science (BS), Electrical and Computer Engineering @ University of California, Santa Barbara From 1993 to 1995 Charles Pryor is skilled in: FPGA, RTL design, SoC, Semiconductors, ASIC, Hardware Architecture, VHDL, Embedded Systems, Debugging, PCB design, Verilog, Digital Signal Processors, Perforce, Agile Project Management, Power Distribution