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Alvin Jee

CTO

Sr. Staff Development Engineer - Advanced Engineering, Biometric Products Division at Synaptics

San Francisco Bay Area

Section title

Alvin Jee's Email Addresses & Phone Numbers

Alvin Jee's Work Experience

Neanderthal Design, LLC

CTO

January 1991 to Present

Synaptics

Sr Staff Development Engineer - Advanced Engineering, Biometric Products Division

March 2015 to Present

Tabula, Inc.

Sr Staff Engineer

July 2007 to March 2015

Alvin Jee's Education

University of California, Santa Cruz

BS MS Ph.D Computer Engineering

1984 to 1996

Alvin Jee's Professional Skills Radar Chart

Based on our findings, Alvin Jee is ...

Self-reliant
Autonomous
Insightful

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Based on our findings, Alvin Jee is ...

52% Left Brained
48% Right Brained

Alvin Jee's Estimated Salary Range

About Alvin Jee's Current Company

Neanderthal Design, LLC

• Responsible for the design and implementation of a suite of design-for-manufacturability (DFM) tools • Performed market analyses, developed business plans and prepared patent filings for software tools for DFM • Prepared and presented DFM lectures to EDA companies, IP vendors, IDMs and fabless semiconductor companies • Responsible for the design and implementation of a software run-time...

Frequently Asked Questions about Alvin Jee

What company does Alvin Jee work for?

Alvin Jee works for Neanderthal Design, LLC


What is Alvin Jee's role at Neanderthal Design, LLC?

Alvin Jee is CTO


What is Alvin Jee's personal email address?

Alvin Jee's personal email address is al****[email protected]


What is Alvin Jee's business email address?

Alvin Jee's business email address is a*****@neander.com


What is Alvin Jee's Phone Number?

Alvin Jee's phone (**) *** *** 886


What industry does Alvin Jee work in?

Alvin Jee works in the Semiconductors industry.


About Alvin Jee

📖 Summary

Computer Engineer with broad experience and expertise in software and hardware who loves to help create innovative and exciting products. Can craft a wide range of software from CAD tools to Linux PCIe kernel drivers; from PERL and Tcl scripts to custom GPIB equipment control applications. Solid understanding of transistor-level and gate-level digital circuit design. I believe that automation and a solid data processing infrastructure are keys to successful endeavors. Random list of things I've worked with in the past in no particular order: • LabVIEW, Matlab, R • Spice circuit simulators • Magic layout editor, Virtuoso, TinyCAD • simvision, ncsim, gtkwaves • dataPower yield management • Sybase, Oracle, mySQL • Mac OSX, Linux, iOS, WIndows, AIX, Solaris, HP/UX, NeXT/OpenStep • CPU's: CDP1802, NS32X32, 68HC11, 68020, 8086, PowerPC • IDE's: Xcode, Eclipse, QT, ProjectBuilder, InterfaceBuilder • QuickBooks • TeX/LaTeX, Postscript • TurboFault ATPG, TetraMax ATPG • GPIB, i2c, SPI, RS232, JTAG, MIPI • Credence Kalos, Agilent 93000, Advantest T2000 testers • EG4080, UF2000 wafer probers • Lot's of oscilloscopes, logic analyzers, power supplies, pulse generators, spectrum analyzers, frequency synthesizers, BERTscopes, DMM's, frequency counters and on and on • Xilinx FPGA's • VHDL, Verilog • TWiki, Confluence • Git, Perforce, CVSCTO @ • Responsible for the design and implementation of a suite of design-for-manufacturability (DFM) tools • Performed market analyses, developed business plans and prepared patent filings for software tools for DFM • Prepared and presented DFM lectures to EDA companies, IP vendors, IDMs and fabless semiconductor companies • Responsible for the design and implementation of a software run-time debugger for Objective-C • Wrote mach kernel drivers and user level software to communicate with QuickCams for video conferencing on NeXT computers From January 1991 to Present (25 years) Sr Staff Development Engineer - Advanced Engineering, Biometric Products Division @ From March 2015 to Present (10 months) Sr Staff Engineer @ Test Lab Manager: designed and outfitted a semiconductor engineering test lab: • Converted an empty room into an ESD-safe, 12-bench, fully equipped IC test lab • Evaluated and acquired test equipment such as: oscilloscopes, high-speed BERT testers, power supplies, logic analyzers, DMM’s, temperature forcers, frequency counters, air compressors and soldering/wire-wrap tools • Ensured that evaluation boards and high-pin count IC sockets functioned correctly Created an Engineering IC Test Platform: created the software, firmware and hardware for a custom, low-cost engineering IC test platform: • enabled rapid silicon verification and characterization by providing circuit designers an easy method for developing sophisticated tests • wrote a Linux-based C++ application for pushing test stimuli to the device-under-test and comparing the responses to expected values - wrote drivers for i2c and GPIB communication to control all bench test equipment for automated testing - wrote a custom Linux kernel PCIe driver to talk to the custom tester board via a 4 lane PCIe Gen 2 link - incorporated a Tcl interpreter to enable complex program flow control and data analysis • created the custom tester board using Tabula’s previous generation 3D PLD. Product Engineering: • generated ATPG scan test patterns to achieve high fault coverage • worked with designers to diagnose high yield fallout and determine corrective actions with either a design change or a foundry change • worked with Test Engineers to build high quality test programs • designed burn-in boards for HTOL testing and qualification From July 2007 to March 2015 (7 years 9 months) Board Member/Treasurer @ Handled all accounting duties using QuickBooks: • invoiced monthly dues • collected payments • handled accounts payable • prepared State and Federal documentation and tax filings From September 2013 to April 2014 (8 months) Staff Product Engineer @ • Implemented an automated yield data management system • Developed and deployed web-based solutions including a Wiki system and several javascript/HTML applications • Managed a team focused on delivering a final product yield of fewer than 200 defects-per-million • Developed a Windows-based, multi-threaded socket-based system for controlling custom memory programmers • Developed memory bitmap conversion utilities From January 2006 to July 2007 (1 year 7 months) MTS @ Product engineer for 3D OTP NAND Flash devices. Set up the dataPower yield management system to monitor test and programming yield for NAND devices. Acquired by SanDisk in 2006. From April 2004 to January 2006 (1 year 10 months) MTS @ • Product manager for Safari™–a set of software tools for analyzing realistic failures in array-based VLSI designs. Safari’s output included fault coverage, fault signatures, diagnostic resolutions and probable defect mechanisms for observed faulty behaviors. - Performed all roles in the product lifecycle including: design, implementation, test, sales, marketing and support. • Created statements of work and project reports for failure analysis consulting contracts • Created and delivered pre-sales technical presentations for prospective clients as well as post-sales training • Managed C and C++ software developers and technical staff locally and globally From February 1999 to November 2002 (3 years 10 months) Director of Engineering @ Developed DFM software that analyzed semiconductor layouts for potential manufacturing faults. Acquired by HPL in 1999. From June 1995 to February 1999 (3 years 9 months) Graduate Researcher @ From 1988 to 1996 (8 years) Intern @ Summer intern in various groups: Design Technology, TestCAD, PDT. From June 1990 to September 1994 (4 years 4 months) Intern @ From 1987 to 1990 (3 years) BS, MS, Ph.D, Computer Engineering @ University of California, Santa Cruz From 1984 to 1996 Alvin Jee is skilled in: Semiconductors, ASIC, Testing, EDA, GPIB, TCL, Engineering, Manufacturing, Mixed Signal, FPGA, IC, Debugging, Verilog, DFT


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In a nutshell

Alvin Jee's Personality Type

Introversion (I), Sensing (S), Thinking (T), Perceiving (P)

Average Tenure

5 year(s), 6 month(s)

Alvin Jee's Willingness to Change Jobs

Unlikely

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