Top Design Engineers in Santa Clara, California

Harpreet Singh

Senior Mechanical Engineer

Santa Clara, California

Senior Mechanical Engineer

CAD Engineer

Senior Mechanical Design Engineer

San Jose State University

Maharshi Dayanand University

Recommendations: 16

Solidworks

Microsoft Excel

CAD

CFD

Solid Modeling

Finite Element Analysis

Microsoft Word

Engineering

Michal Kozak

Senior Staff Software Engineer

Santa Clara, California

Senior Staff Software Engineer

Software Design Engineer

System Analyst and Architect

Web service developer (internship)

West Pomeranian University of Technology in Szczecin

Recommendations: 14

OOP

Distributed Systems

UML

Design Patterns

Java

Software Development

C++

i*****@o2.pl

Brian Hook

ASIC Design Engineer

Santa Clara, California

ASIC Design Engineer

Intern Software Engineer

ASIC Design Engineer

Design Verification Engineer

ASIC Design Engineer

Northeastern University

University of Central Florida

Recommendations: 7

SystemVerilog

Perl

Python

Verilog

SoC

Functional Verification

ASIC

RTL design

e****[email protected]

Frank Wu

Senior Electrical Engineer | Project Manager

Santa Clara, California

Senior Electrical Engineer | Project Manager

Senior Electrical Engineer

Hardware Design Engineer

Senior Staff Hardware Engineer

Senior Electrical Engineer

San Jose State University

Hunan University

Hunan University Affiliated Middle School

Recommendations: 7

Embedded Systems

PCB Design

Testing

Electronics

Hardware Architecture

Manufacturing

Analog

Wireless

f****[email protected]

Sri M

Analog/Mixed Signal Design Engineer II

Santa Clara, California

Analog/Mixed Signal Design Engineer II

Electronic Design Engineer

Stanford University

Recommendations: 7

Mixed Signal

CMOS

Verilog

Analog

BiCMOS

Cadence Virtuoso

TCL

Analog Circuit Design

f****[email protected]

Alireza Atrvash

Staff Design Engineer

Santa Clara, California

Staff Design Engineer

Senior Controls Engineer

Senior Design Engineer

Electrical - Control Systems Engineer

Automation - Control Systems Engineer

Senior Control System ENGINEER (Business Development Dept)

Electrical & Control System Engineer

Electrical ENGINEER

Engineering Manager, Design and Technical Programs

Manager of Electrical Engineering

University of Tehran

Alborz High School

Recommendations: 6

DCS

PLC

SCADA

Commissioning

Factory

Engineering

Project Engineering

PCS7

Khaled PhD

Sr. Antenna Design Engineer

Santa Clara, California

Sr. Antenna Design Engineer

Antenna Lead

Distinguished Antenna RF Engineer at Ruckus Wireless

Principal Antenna RF Design Engineer (Jaybird Wearable)

The Ohio State University

University of South Florida

University of Michigan - Rackham Graduate School

Recommendations: 6

Antenna Design

Antennas

HFSS

PCB design

CST Microwave Studio

FEKO

ads

k****[email protected]

Ali Baig

Software Design and Test Engg

Santa Clara, California

Software Design and Test Engg

Sr. Engineering Manager

Software Engineer

Software Developer

Quality Engineering Manager II

Verification Design Engineer

Software Developer Manager II

Cornell University

GIK Institute of Engineering Sciences and Technology

Recommendations: 5

Software Development

Quality Control

C++

Perl

Agile Methodologies

Software Engineering

Testing

Test Automation

Felix Njeh

Systems Engineer

Santa Clara, California

Systems Engineer

Unix (Irix) Systems Administrator

Systems Engineer

Principal Systems Engineer

Enterprise Architech/Systems Engineer

Systems Design Engineer

Bowie State University

University of Ottawa

Recommendations: 4

Cloud Computing

Data Center

Solution Architecture

Integration

TCP/IP

Security

Perl

Network Architecture

f*****@yahoo.com

Mayuresh Ektare

Vice President Of Product Management

Santa Clara, California

Vice President Of Product Management

Director, Product Management & UX

Sr. UI Design Engineer

Director - HiveManager NG (Acquired by Extreme Networks)

Sr. Human Factors Engineer

Clemson University

Nagpur University

Recommendations: 4

Usability Testing

User-centered Design

Heuristic Evaluation

Product Management

User Experience

Agile Methodologies

User Interface Design

User Interface

Sameer Kolte

ADAS Engineer: Vehicle Motion Control

Santa Clara, California

ADAS Engineer: Vehicle Motion Control

Senior Systems Engineer, Self Driving

Engineering Intern

Product Design Engineer

Controls Engineer

Senior ADAS Engineer: Vehicle Motion Control

Team Lead

University of Michigan

University of Mumbai

Recommendations: 4

Automobile

System Design

Vehicle Dynamics

Control Systems Design

Vibration Control

Mathematical Modeling

Design for Manufacturing

Geometric Dimensioning & Tolerancing

Nandith Chandy

Test Engineer

Santa Clara, California

Test Engineer

Mechanical Engineer

Design Engineer

Research Assistant

Project Assistant

Drive Unit Test and Validation Engineer

Senior functional test engineer, Thermal Systems

Thermal Engineer

Iowa State University

M.S. Ramaiah Institute Of Technology

Nitte meenakshi institute of technology

Recommendations: 3

Matlab

ANSYS

Fluent

SolidWorks

CATIA

Solid Edge

Pro Engineer

FTIR

Priyanka S.

Software Engineer - Mobile

Santa Clara, California

Software Engineer - Mobile

Enterprise Security Application Developer

Member of Technical Staff

Android Developer

Design Engineer

Senior Software Engineer

Engineering Manager

Georgia State University

Biju Patnaik University of Technology

Recommendations: 3

Java

XML

Eclipse

Android

Web Services

Testing

Mobile Applications

JSP

Priyanka Manjarekar

Electrical Engineer

Santa Clara, California

Electrical Engineer

IT Consultant (Student Assistant)

Signal Integrity Engineer

Electrical Validation Engineer

Senior Hardware Design Engineer

Graduate Assistant/Office Manager

Binghamton University

Bharati Vidyapeeth, India

Recommendations: 3

Preetham Duggishetti

Design Engineer II

Santa Clara, California

Design Engineer II

Sr.Design Verification Engineer

Graduate Student

Arizona State University

MVSR Engineering College(Osmania University)

Recommendations: 3

Digital Design

VHDL

Layout

Verilog

FPGA

Analog Design

Mixed Signal

Ratnendra Pandey

IC Design Engineer

Santa Clara, California

IC Design Engineer

Hardware Engineer

Guest Lecturer

Project Associate

Member of Technical Staff

Applications Engineer

Silicon Design Engineer

Design Consultant RTL-Physical Design

Physical Design Engineer

Staff Corporate Application Engineer

San Jose State University

South Dakota State University

Punjab Engineering College

Recommendations: 3

ASIC

Static Timing Analysis

RTL design

TCL

Verilog

EDA

Debugging

Semiconductors

Fengming Zhang

Hardware Design Internship

Santa Clara, California

Hardware Design Internship

Principal Physical Design Engineer

Senior Hardware Engineer

Senior Member of Technical Staff

Member of Technical Staff

Hardware Design Engineer

Senior Technical Leader

Principal Hardware Engineer

Northeastern University

Beijing University of Chemical Technology

Recommendations: 3

Verilog

EDA

SPICE

Static Timing Analysis

Physical Design

Microprocessors

CMOS

Cadence

z****[email protected]

f****[email protected]

Krishna Sumanth

DV @ Oracle

Santa Clara, California

DV @ Oracle

Senior Engineer - DV

Member Technical Staff

ASIC DV Engineer

GPU DV

Design Engineer

International Institute of Information Technology

Recommendations: 3

ASIC

Debugging

Semiconductors

Static Timing Analysis

Open Verification Methodology

g****[email protected]

Nat Collins

Analog Layout Engineer

Santa Clara, California

Analog Layout Engineer

CEO and Co-founder

Electronic Engineer / Contractor

Laser, Optics, and Materials Researcher / Contractor

Director of Product Engineering

Product Design Engineer

Senior Semiconductor Technology / Process Integration Engineer

Senior Process Integration Engineer

Boston University

Recommendations: 3

Project Management

CMOS

Testing

Process Integration

Semiconductors

Analog

Cadence Virtuoso

Amirtha Kasturi

Principal Engineer

Santa Clara, California

Principal Engineer

Senior Engineer

Intern Engineer

Design Architectural Engineer

Consultant, VLSI Verification

AMTS VLSI Design Engineer

Teaching Assistant

University of Pittsburgh

University of Madras

Recommendations: 3

ASIC

SoC

Semiconductors

FPGA

Verilog

SystemVerilog

PERL

Simulations

Apala Trivedi

Test engineer

Santa Clara, California

Test engineer

ASIC verification engineer

Digital Design Engineer

Design Verification Engineer

Santa Clara University

L.D. College of Engineering

Recommendations: 2

FPGA

Debugging

Perl

ASIC

Verilog

Functional Verification

System Verilog

Integrated Circuit Design

Preetish Shiroor

MTS

Santa Clara, California

MTS

Software Engineer 3

mobile intern

Programmer

Technical Specialist

Senior s/w design engineer

Software Design Engineer

University of Southern California

Visvesvaraya Technological University

Recommendations: 2

Software Development

Embedded Systems

Embedded Software

Agile Methodologies

C++

ClearCase

Saurabh Adya

Software Engineer R&D, Principal

Santa Clara, California

Software Engineer R&D, Principal

Software Engineer R&D, Staff

ML Research Scientist/Manager, Principal(V)

Graduate Student Research Assistant

Software Engineer R&D, Managing Architect

Integrated Circuit Design Engineer

Software Engineer R&D, Sr II

University of Michigan

KREC (NITK), Surathkal

Recommendations: 2

Software Development

Convex Optimization

Mathematics

Combinatorial...

Optimizations

Algorithms

Numerical Analysis

Data Structures

Prahallad Iyengar

Research Assistant

Santa Clara, California

Research Assistant

Staff Mechanical Engineer

Graduate Student

Mechanical Design Engineer

Principal

Sr. Product Design Engineer

Research Assistant

Mechanical Engineer, R&D

Teaching Assistant

Staff Mechanical Engineer

Mechanical Design Engineer

Stanford University

University of California, Berkeley

Recommendations: 2

ANSYS

Fluid Mechanics

Thermodynamics

Solidworks

AutoCAD

Finite Element Analysis

CFD

Mechanical Engineering

Randy Persaud

Principal Software Engineer

Santa Clara, California

Principal Software Engineer

Physical Design Engineer

Deep Learning Software Engineer

Senior Software Engineer

Graduate Electrical Engineering Intern

Research and Development Engineer

Teaching Assistant

University of Minnesota

Recommendations: 2

Java

x86 Assembly

Perl

C++

TCL

Scheme

Visual Basic

d****[email protected]

Conrad Salinas

Senior Design Engineer

Santa Clara, California

Senior Design Engineer

Firmware Engineer

Electronics Engineer (Robotics)

Senior Research And Development Engineer

Summer Intern

Software Test Engineer

Embedded Programmer

Embedded Systems Engineer, Robotics Automation

Independent Engineering Consultant

University of California, San Diego

Southwestern College

Recommendations: 2

Embedded Software

Microcontrollers

Matlab

Pspice

Python

ARM

Software Engineering

Sanjay Gurlahosur

Member technical staff

Santa Clara, California

Member technical staff

Member technical Staff

Analog Design Manager

Member Group technical Staff

Principle Design Engineer

Senior analog IC design Engineer

Design engineer

Principle Design Enginner

Principle Design Engineer

Staff Design Engineer

B V Boomareddi college of engineering and technology, Hubli, India

Beynon smith high school, Belgaum, Karnataka, India

Recommendations: 2

Analog Design

System knowledge on power management designs

Power Management

Analog Circuit Design

Mixed Signal

CMOS

Integrated Circuit Design

Srinivas Maddula

Graduate Teaching Assistant

Santa Clara, California

Graduate Teaching Assistant

Fall Intern

Analog Design Engineer

Hardware Design Engineer

Arizona State University

Birla Institute of Technology and Science

Birla Institute of Technology and Science, Pilani

Recommendations: 2

Communication Protocols

Cadence

Data Structures

Formal Verification

ASIC

Verilog

Simulations

Shyam Nukala

Tech Lead & Member of Technical Staff

Santa Clara, California

Tech Lead & Member of Technical Staff

Software Engineer

Principal Software Engineer

Sr. Software Engineer

Sr Design Engineer

Tech Lead

Principal Software Engineer

Staff Software Engineer, QBO Platform

Indian Institute of Technology, Bombay

Recommendations: 2

Java

Concurrent Programming

Multithreading

REST

Usability

Application Monitoring

Open Source

C++

Aldrin Paynter

Test Engineer

Santa Clara, California

Test Engineer

Analog Design Engineer

Test Development Engineer

Research Assistant (solar house)

CO-OP Student Worker Cross Functional

Santa Clara University

University of Mumbai

Recommendations: 2

Analog Circuit Design

Digital Electronics

Analog

Testing

Electronics

Verilog

Mixed Signal

Ravi Magadum

Physical Design Engineer

Santa Clara, California

Physical Design Engineer

Physical Design and Mask Design Engineer

Physical Design and Mask Layout Design Engineer

Arizona State University

Gogte Institute of Technology,Belgaum

RL science institute,Belgaum

Recommendations: 1

Cadence Virtuoso

Analog

VLSI

CMOS

Mixed Signal

LVS

DRC

Virtuoso

u****[email protected]

Nikhilesh Bhagat

Graduate Student Intern

Santa Clara, California

Graduate Student Intern

Product Development Intern

Digital Hardware Design Intern

Graduate Research Assistant| VLSI

ASIC/ FPGA Design Engineer

Project Trainee

Digital Signal Processing Engineer

Digital Design Engineer

Wireless Digital Design Engineer

San Diego State University-California State University

University of Pune

St. Patrick's High School.

Recommendations: 1

VLSI

Verilog

VHDL

Matlab

RTL Design

Static Timing Analysis

Cadence

Sai Seshabhattar

Staff Application Engineer Emulation

Santa Clara, California

Staff Application Engineer Emulation

Application Consultant, Sr I

Application Consultant

Staff-I IC Design Engineer

Hardware design verification engineer

PDE- Co-op

The University of Texas at Arlington

Jawaharlal Nehru Technological University

Recommendations: 1

Logic Design

RTL coding

Computer Arithmetic

Functional Verification

RTL design

Hardware Architecture

Integrated Circuit...

LYON (yongsoon) lee

ASIC/FPGA Design Engineer

Santa Clara, California

ASIC/FPGA Design Engineer

FPGA / Communication Chip Design Engineer

ASIC/FPGA Design Engineer

The University of British Columbia

University of Saskatchewan

Recommendations: 1

Verilog

ASIC

FPGA

Digital Signal Processors

SoC

Semiconductors

ARM

system verilog

l*****@utocon.com

l*****@kopin.com

Navin Mohan

Application Engineer

Santa Clara, California

Application Engineer

Hardware Engineer

Intern - Hardware Engineering (Analog)

Staff Design Engineer

Silicon Architect Engineer (ASIC Design and Verification)

Analog Engineer/Component Design Engineer

Teaching Assistamt

SOC/ASIC Design Engineer

Arizona State University

Birla Institute of Technology and Science, Pilani

Sankara Vidhyalaya School

Recommendations: 1

VLSI

Verilog

Joe Wei

Security Engineer

Santa Clara, California

Security Engineer

Principal Member of Technical Staff

Sr. Software Engineer

R&D Engineer

Java Card Software Engineer

Software Engineer

Software QA Engineer

Design Engineer

University of California, Los Angeles

Université du Québec à Trois-Rivières

Recommendations: 1

Mobile Technology

Java

Eclipse

Android

Smart Cards

JavaCard

Software Development

NFC

Umesh Pandey

Senior Engineer

Santa Clara, California

Senior Engineer

Engineer

Principal Design Engineer

Staff Engineer

Senior Engineer

Senior Software Engineer

Indian Institute of Technology, Bombay

University of Mumbai

Recommendations: 1

Embedded Systems

Apache Spark

Digital Signal Processors

H.264

Debugging

Firmware

RTOS

Assembly Language

u****[email protected]

Nathan Womack

Applications Engineer

Santa Clara, California

Applications Engineer

Sr. Field Applications Engineer

Field Applications Engineer

Digital Design Engineer

Principal Engineer, R&D

Principal Applications Engineer

The Johns Hopkins University

The University of Texas at Dallas

Recommendations: 1

Verilog

VHDL

SystemC

C++

Synplify

Python

TCL

Vim

Annie Chang

Technical Program Manager - Resource Management and Cost Optimization for YouTube Storage Capacity

Santa Clara, California

Technical Program Manager - Resource Management and Cost Optimization for YouTube Storage Capacity

Senior Technical Program Manager

Technical Marketing Intern

Technical Program Manager - Capacity Planning and Growth Forecasting for New Regions

Ultrabook™ Marketing Strategy Intern

Systems Design Engineer

Silicon Valley Intern

Massachusetts Institute of Technology - Sloan School of Management

Santa Clara University

Recommendations: 1

Semiconductors

ASIC

Embedded Systems

SoC

Product Management

Firmware

Cross-functional Team...

Debugging

Manoj Yadav

Sr. Design Engineer

Santa Clara, California

Sr. Design Engineer

Research Engineer (EII)

Research Engineer (EI)

Staff Engineer

Design Engineering Manager

Sr. Staff Design Engineer

Principal Engineer

Design Engineer

University of Minnesota-Twin Cities

Santa Clara University - Leavey School of Business

Indian Institute of Technology, Roorkee

Recommendations: 1

Market Research

Competitive Analysis

Pricing

Business Valuation

RTL design

Verilog

Functional Verification

Logic Synthesis

Ashwin Badrinarayanan

MTS Applications

Santa Clara, California

MTS Applications

Senior MTS: Applications

Intern - RF Hardware Design Engineer

Contractor - RF Hardware Engineer

Associate MTS Applications

Hardware Development Intern

The University of Texas at Dallas

SASTRA University

Recommendations: 1

SPICE

SoC

Spectre

PCB design

Cadence

Circuit Design

Low-power Design

v****[email protected]

Daryoosh Rejaly

Principal Electrical Engineer

Santa Clara, California

Principal Electrical Engineer

Sr. Member Technical Staff

Senior Staff Electrical Engineer

Lead Lidar Engineer

Sr. RF Design Engineer

Senior Electrical Engineer

RF Design Engineer

Senior RF Design Engineer

RF Design Engineer

Ferdowsi University of Mashhad

Iran University of Science and Technology

Recommendations: 1

d****[email protected]

Chunli Cai

Sr. Principal Engineer

Santa Clara, California

Sr. Principal Engineer

Sr. staff Analog Design Engineer

University of Southern California

South China University of Technology

Recommendations: 1

Wira Gunawan

Test Development Engineer

Santa Clara, California

Test Development Engineer

Senior Staff Design Engineer

University of Illinois at Urbana-Champaign

The Ohio State University

Recommendations: 1

ASIC

Verilog

Low-power Design

TCL

Primetime

Debugging

SoC

Manickaraja Vivekanandan

Asic verification engineer

Santa Clara, California

Asic verification engineer

Principal Engineer

Senior Staff Engineer

Staff Engineer

Senior Verification Design Engineer

Senior Engineer

PSG College of Technology

Oxford Matriculation Hr Sec School,Sivagangai

Anna University

Recommendations: 1

SystemVerilog

ASIC

Verilog

Functional Verification

VLSI

Samira Bashiri

Analog Engineer

Santa Clara, California

Analog Engineer

Mixed Signal Design Engineer

Research student

Reaserch student

Software developer engineer

Carleton University

Shahid Beheshti University

Recommendations: 0

Peter Kovacs

DSP Engineer

Santa Clara, California

DSP Engineer

Senior Wireless RTL Design Engineer

Wireless DSP engineer

Wireless DSP-engineer

Budapesti Mûszaki és Gazdaságtudományi Egyetem

Recommendations: 0

SoC

FPGA

ASIC

Verilog

ModelSim

Functional Verification

Integrated Circuit Design

RTL design

Alex Neduva

Principal Test Engineer

Santa Clara, California

Principal Test Engineer

Senior MTS

Senior Test Engineer, Circuit Design Engineer

Staff Test Engineer

HW Principle Engineer

Senior Application Engineer

Moscow Telecommunication University

Technion - Israel Institute of Technology

Recommendations: 0

Test Engineering

Circuit Design

Product Management

Semiconductors

VLSI

SRAM

Engineering

DFT

Ziad Abu-Lebdeh

Technical Lead, VP Research & Development

Santa Clara, California

Technical Lead, VP Research & Development

Sr. Manager, System I/O IP Group

Sr. FPGA Design Engineer

Missouri University of Science and Technology

Recommendations: 0

Product Development & Management

Team Building and Leadership

IP Legal Managment

Strategic Planning

Project Managment

FPGA

Semiconductors

z****[email protected]

Qiang Yu

Senior RF/mmWave IC Design Engineer

Santa Clara, California

Senior RF/mmWave IC Design Engineer

Staff RF/mmWave IC Design Engineer

Senior RF Design Engineer

Research Assistant

University of Virginia

Louisiana State University

Shanghai Jiao Tong University

Recommendations: 0

Matlab

Simulations

RF test

RFIC design

Mixed signal design

Micro-machining

Strain Sensor

Sensors

q*****@virginia.edu

Alex Wapniarski

Software Engineer II

Santa Clara, California

Software Engineer II

Assistant Instructor

Mechanical Design Engineer

University of California, Berkeley

Recommendations: 0

Pro/Engineer

AutoCAD

Solidworks

3D Studio Max

Sheet Metal Design

Photoshop

Illustrator

CAD

Swapnil Dwivedi

Verification Engineer

Santa Clara, California

Verification Engineer

Senior R&D Software Engineer

Network Design Engineer

Senior Architect

Senior Software Engineer

Founder

University of Iowa

Institute of Engineering and Technology

The Air Force School (TAFS), Subroto Park

Recommendations: 0

Algorithm Optimization

Design Verification

Java

Verilog

SystemVerilog

VHDL

Assembly Language

Perl

Samrat Bandgar

Senior Software Engineer

Santa Clara, California

Senior Software Engineer

Staff Software Engineer

Senior Principal Development Engineer

Technical Architect

Trainee Engineer

Associate Design Engineer

Seed Infotech

Shivaji University

S M Lohia Highschool, Kolhapur

Recommendations: 0

Sarah Gerweck

Software Developer

Santa Clara, California

Software Developer

Chief Technology Officer & Cofounder

Integration Engineer

Principal Engineer

Chief Architect & Cofounder

Architect, Advertising Insights

Senior Software Design Engineer

Java Developer

Recommendations: 0

Java Enterprise Edition

Databases

Distributed Systems

Analytics

Java

Software Design

t****[email protected]

Jihoon Kim

Software Engineer

Santa Clara, California

Software Engineer

Full Chip Layout Design Automation Intern

Programmer

Software Engineer

Component Design Engineer

Design Automation Engineer

Intern/Researcher with SMDL group

University of California, Los Angeles

University of California, Berkeley

Stanford University

Recommendations: 0

Perl

EDA

TCL

Verilog

SPICE

C++

Java

Oliver Bowen

Principal Digital Designer

Santa Clara, California

Principal Digital Designer

Project Electrical Engineer

Intern

Senior Hardware Engineer

VLSI Design Engineer

Digital Systems Engineer

Digital Design Engineer

Imperial College London

Lafayette College

Recommendations: 0

FPGA

Verilog

VHDL

Xilinx

Matlab

C++

Python

o****[email protected]

Zimo Li

Research Student

Santa Clara, California

Research Student

Design Engineer

Software Engineer

Research Assistant

Software Developer Engineer

Software Developer Internship

University of Toronto

Recommendations: 0

Verilog

C++

Matlab

FPGA

Perl

Python

ASIC

z****[email protected]

Ning Chen

SSD Architect

Santa Clara, California

SSD Architect

Product Design Engineer

Principal Engineer

Principal System Architect

Intern

Project Manager

Design Engineer

Lehigh University

Tsinghua University

Recommendations: 0

ASIC

SSD

Firmware

ARM

Digital Signal Processors

Device Drivers

Verilog

Embedded Systems

Anubhav Gupta

CTO, IoT & Wearables

Santa Clara, California

CTO, IoT & Wearables

Director of Product Management, Edge IoT & Wearables

Director- Strategic Business Development & Ecosystem Partnerships (IoT)

Product Manager (Automotive ADAS & Infotainment Microprocessors)

Engineering Manager & SoC Architect, Analog/ Mixed Signal Design

Senior Analog Design Engineer

The University of Texas at Austin - Red McCombs School of Business

Indian Institute of Technology, Bombay

Recommendations: 0

Product Marketing

Product Management

Business Strategy

Financial Valuation

Corporate Finance

Business Management

Project Planning

Sales Management

Kushal Dave

ASIC Design Engineer

Santa Clara, California

ASIC Design Engineer

Graduate Student

Sr. Design Engineer

Staff Design Engineer

Design Engineer - Co-op

San Jose State University

Gujarat University

Recommendations: 0

d****[email protected]

Shougui Yang

ASIC Verification Engineer

Santa Clara, California

ASIC Verification Engineer

Senior ASIC Design Engineer

FPGA Designer

Logic Verification Engineer (Intern)

SoC Verification Lead, Staff Engineer

ASIC Design Verification Engineer

SoC Design Research Assistant

Peking University

Recommendations: 0

OVM

UVM

FPGA

Verilog

System Verilog

Verification

DDR SDRAM

C++

y****[email protected]

Sambhav Jain

Design Engineer

Santa Clara, California

Design Engineer

Senior Machine Learning Engineer

Undergraduate Researcher

Research Intern

Staff Machine Learning Engineer

Research Assistant

Graduate Research Assistant

Stanford University

National Institute of Technology Tiruchirappalli

Don Bosco School, Egmore, Chennai

Recommendations: 0

Bong Kim

Sr. Software Engineer

Santa Clara, California

Sr. Software Engineer

Software Engineer

Senior Software Design Engineer

SW Engineer Staff

Software Engineer

Sr. Software Engineer

The University of Texas at Austin

Recommendations: 0

Lavanya Subramanian

Staff Research Scientist

Santa Clara, California

Staff Research Scientist

Research Intern

ASIC Design Engineer

Research Scientist

SoC Architect at Facebook Reality Labs

Graduate Student Researcher

Research Intern

Silicon Performance Architect

Carnegie Mellon University

Madras Institute of Technology, Anna University

Saraswathi Vidyalaya

Recommendations: 0

C++

Analysis

Verilog

ASIC

VLSI

Embedded Systems

Python

l****[email protected]

Raghu Bulusu

Firmware Engineer

Santa Clara, California

Firmware Engineer

Sr. Firmware Engineer

Design Engineer

Engineering Manager/Software Development Lead (Silicon Architecture)

Engineering Manager

Illinois Institute of Technology

Jawaharlal Nehru Technological University

Recommendations: 0

Firmware

Debugging

Microcontrollers

Embedded Systems

USB

Device Drivers

Embedded Software

Computer Architecture

Wanghua Wu

RFIC Senior Manager

Santa Clara, California

RFIC Senior Manager

RF/Analog IC Design Engineer

Analog/RF IC Engineer

Design Engineer Intern

Research Assistant (PhD candidate)

Delft University of Technology

Fudan University

Recommendations: 0

CMOS

Analog Circuit Design

Circuit Design

Analog

Matlab

Cadence Virtuoso

Integrated Circuit Design

Alan Phan

Senior Design Engineer

Santa Clara, California

Senior Design Engineer

Senior Staff Design Engineer

Senior Applications Engineer

FPGA Design Engineer

Staff Design Engineer

San Jose State University

Recommendations: 0

Elaine Yu

Design Verification Engineer

Santa Clara, California

Design Verification Engineer

Staff Design Engineer

ASIC Engineer

Design Verification Engineer

Design Verification Consultant

Design Verification Engineer

Engineering Consultant

Stanford University

Recommendations: 0

ASIC

VLSI

SoC

RTL design

SystemVerilog

y****[email protected]

Kangwei Mao

Applications Engineer

Santa Clara, California

Applications Engineer

Power Electronics Manager

Senior Electrical Engineer, Power Electronics

Co-op Power Electronics Engineer

Power Electronics Engineer Intern

Senior Application Engineer

Automotive Marketing and Applications

Senior System Design Engineer

University of Michigan

Tongji University

Recommendations: 0

Matlab

Circuit Design

Simulink

C++

Circuit Simulation

Analog Circuit Design

PCB design

m*****@umich.edu

Vishal Mehta

Senior ASIC Design Engineer

Santa Clara, California

Senior ASIC Design Engineer

ASIC Design Engineer

Project Assistant

ASIC Intern

University of Wisconsin-Madison

Indian Institute of Technology (Banaras Hindu University), Varanasi

The Indian School, Bahrain

Our Own English High School, Dubai, UAE

Recommendations: 0

RTL design

SoC

Verilog

ASIC

Debugging

Timing Closure

Functional Verification

VLSI

v****[email protected]

Syed Nazar

Electrical Engineering Manager

Santa Clara, California

Electrical Engineering Manager

Hardware Design Engineer

Operations Support Intern, Silicon Image

Product Application Engineer

San Jose State University

Recommendations: 0

Verilog

C++

Xilinx ISE

Cadence

Matlab

Altera Quartus

Synopsis

Microsoft Office

Alex Liberman

Senior Software Engineer

Santa Clara, California

Senior Software Engineer

Software Engineer

Senior Software Engineer

Software Design Engineer

Senior Software Engineer

Senior Programmer

Cornell University

Recommendations: 0

Xbox 360

Console

Computer Graphics

Game Development

C++

Gameplay Programming

Software Engineering

Ko-Chung Tseng

ASIC Design Manager

Santa Clara, California

ASIC Design Manager

Research Assistant

Teaching Assitant in EE577b (VLSI System Design)

Staff Design Engineer

Senior ASIC Design Engineer

Teaching Assistant in EE477L (MOS VLSI Circuit Design)

University of Southern California

Recommendations: 0

Verilog

SystemVerilog

Matlab

C++

Java

JavaScript

Cadence Ocean Script

Python

k****[email protected]

Yi-Chen Kuo

Opto-mechanical Engineer

Santa Clara, California

Opto-mechanical Engineer

Product Design Engineer

Senior Mechanical Engineer (axial fan design)

Product Design Engineer

Thermal Engineer

Mechanical Engineer (axial fan design)

Specialist 2 (Product Design Engineer)

Carnegie Mellon University

National Chiayi University

Recommendations: 0

Ansys ( APDL, Fluent, Gambit, Workbench)

Matlab

Pro Engineer

Unigraphics

Flotherm

Solidworks

Autodesk ( CAD, Sketchbook, Inventor, Simulation)

Minitab

y****[email protected]

Lin Shi

Intern

Santa Clara, California

Intern

Staff Software Engineer

Software Engineer

Apprentice Manager

Research & Design Engineer

Senior Software Engineer

University of Illinois at Urbana-Champaign

New York University

Fudan University

Recommendations: 0

Python

C++

Computer Graphics

Software Development

Programming

Algorithms

SQL

Hui Chen

Senior Applications Engineer/ Hardware Validation Engineer

Santa Clara, California

Senior Applications Engineer/ Hardware Validation Engineer

Analog Design Engineer

Silicon Validation Engineer

Senior System Engineer

Interim Engineering Intern

Texas A&M University

Huazhong University of Science and Technology

Recommendations: 0

Cadence Virtuoso

CMOS

Simulink

Circuit Design

VLSI

Pspice

Analog

Verilog

Sarvesh Bang

Circuit Design Intern

Santa Clara, California

Circuit Design Intern

Lead Analog/Mixed Signal Design Engineer

Analog/ Mixed Signal Research Assitant

Analog/Mixed Signal Design Engineer

Analog Design Engineer

Senior Analog/Mixed Signal Design Engineer

Oregon State University

Birla Institute of Technology and Science, Pilani

Recommendations: 0

Analog

Mixed Signal

Power Management

DC-DC

Backlit Displays

LED Drivers

High speed regulator design

SoC

Teddy Demilew

Sr. iOS Developer

Santa Clara, California

Sr. iOS Developer

Student Researcher/Intern

Staff Software Engineer

Software Engineer

Cofounder and Lead iOS Developer

iOS Developer. Software/Firmware Design Engineer

University of California, Santa Cruz

San Jose State University

University of California, Santa Cruz

Recommendations: 0

iOS

Swift

Objective-C

HTML5

CSS

JavaScript

Ionic Framework

jQuery Mobile

t****[email protected]

Madhan Jaganathan

Principal Manager

Santa Clara, California

Principal Manager

Asic and Systems Design/Firmware Engineer

Director, Wireless Engineering

Systems Lead

Design Engineer

University of California, Santa Cruz

Anna University

Recommendations: 0

DSP

Verilog

Algorithms

Perl

Embedded Systems

SoC

Firmware

Tsung-Hsueh Lee

Senior Analog Design Engineer

Santa Clara, California

Senior Analog Design Engineer

Graduate Research Assistant

Graduate Teaching Assistant

Research Associate

Graduate Research Assistant

Graduate Teaching Assistant

Staff Analog Design Engineer

University of Maryland College Park

National Taiwan University

Recommendations: 0

Matlab

Signal Processing

Analog Circuit Design

FPGA

PCB design

Cadence

Digital Circuit Design

Integrated Circuit Design

t****[email protected]

Arvind Venkat

Sr. Electronics Design Engineer

Santa Clara, California

Sr. Electronics Design Engineer

EE System Integrity Engineer - Product Integrity

Application Engineer - Advanced Technologies and Development

Systems Engineer

Applications Engineer - System & Applications

Rochester Institute of Technology

Visvesvaraya Technological University

Recommendations: 0

Semiconductors

Cadence

Simulations

Verilog

SystemVerilog

Analog Circuit Design

Microcontrollers

ModelSim

Liang Zhou

Senior RTL Design Engineer

Santa Clara, California

Senior RTL Design Engineer

ASIC Engineer 3

MTS ASIC Design Engineer

Design/Verification Intern

University of Arkansas at Fayetteville

Hubei University

Recommendations: 0

Computer Architecture

k****[email protected]

Ryan Ernst

Kernel Design Engineer

Santa Clara, California

Kernel Design Engineer

Software Engineer

Software Design Engineer

California Polytechnic State University-San Luis Obispo

Recommendations: 0

Distributed Systems

Hadoop

Scalability

r*****@iernst.net

Gouri Landge

Sr Staff Design Engineer

Santa Clara, California

Sr Staff Design Engineer

Principal Engineer

Design Engg

University of California, Davis

Savitribai Phule Pune University

Recommendations: 0

g****[email protected]

Rohit Taneja

Server Platform performance Engineer - Big Data solutions

Santa Clara, California

Server Platform performance Engineer - Big Data solutions

Senior Embedded Design Engineer

Master Thesis

Graduate Research Assistant

Interim Engineering Intern

Senior Solutions Architect

Engineer

Embedded Application Engineer

Lead - ML Infrastructure

Graduate Teaching Assistant

North Carolina State University

MAIT

Recommendations: 0

Ying Huang

Research Assistant

Santa Clara, California

Research Assistant

Assistant Radiation Safety Officer

Senior ASIC Design Engineer

Research Assistant

Teaching Assistant

University at Buffalo

Huazhong University of Science & Technology

Recommendations: 0

Cadence Virtuoso

Spices

C/C++, Verilog HDL, VHDL

Shell

Analog Circuit Design

Optical and CCD Detector Design

FPGA/CPLD, MCU, DSP

Circuit Design

Xinyu Yi

Senior Staff Design Engineer

Santa Clara, California

Senior Staff Design Engineer

Embedded system development Assistant Engineer

Web Developer / Software engineer

University of Pittsburgh

Huazhong University of Science and Technology

Recommendations: 0

Cadence

VHDL

Analog Design

Digital Design

Computer Architecture

Altera Quartus

Xilinx

FPGA

Pang-Chen Sun

Hardware Design Engineer

Santa Clara, California

Hardware Design Engineer

Principal optical engineer

Optical Engineer/manager

Product Manager

University of Michigan

National Chiao Tung University

Recommendations: 0

Photonics

Shashank Kulkarni

CPU Digital Design Engineer

Santa Clara, California

CPU Digital Design Engineer

Physical Design Engineer Intern

The University of Texas at Dallas

Visvesvaraya Technological University

Recommendations: 0

Verilog

IC Compiler

Synopsys Primetime

Cadence Virtuoso

ModelSim

Xilinx

Perl

VLSI

Jongseok Lee

Contractor - FPGA Engineer

Santa Clara, California

Contractor - FPGA Engineer

FPGA Design Engineer

Digital Logic Design Intern

Sr. Digital Design Engineer

University of Southern California

Sejong University

Recommendations: 0

Sreedhar Chikoti

Sr. ASIC Design Engineer

Santa Clara, California

Sr. ASIC Design Engineer

University of Southern California

University of Mumbai

Recommendations: 0

ASIC

Computer Architecture

RTL design

Verilog

SystemVerilog

Static Timing Analysis

VLSI

SoC

Muhammad Abdelghaffar

System Design Engineer

Santa Clara, California

System Design Engineer

PhD Candidate/ Graduate Student Researcher

Research Assistant at the Christian Doppler Lab

System Design Engineer

University of California, Irvine

Cairo University

Recommendations: 0

RTL design

VHDL

Verilog

Perl Script

C++ Language

Wireless Communications Systems

Digital Signal Processing

Low Power Systems

Pedram Payandehnia

Intern

Santa Clara, California

Intern

M.Sc. Student at University of Tehran

Design Engineer

Intern

Research Assistance

Senior Design Engineer

College of Engineering

Oregon State University

University of Tehran

Recommendations: 0

Junjia Li

RF Manager

Santa Clara, California

RF Manager

RF/Wireless Development Engineer

RF Design Engineer

Instructor

Embedded System Engineer

Research Associate

Graduate Research Assistant

Texas A&M University

Nanjing University

Recommendations: 0

Matlab

Labview

C++

VHDL

Verilog

LTSpice

Agilent ADS

l****[email protected]

Hendra Soeleman

Hardware Engineer

Santa Clara, California

Hardware Engineer

Principal Hardware Engineer

Circuit Design Engineer

Technical Consultant

Co-Lead/Facilitator

Sr Circuit Design Engineer

Principal Consultant

Purdue University

The University of Texas at Austin

Recommendations: 0

Sudhir Vijay

Graduate Research Assistant

Santa Clara, California

Graduate Research Assistant

Graduate Teaching Assistant

Graduate Research Assistant

Member of Technical Staff

Student Intern

Design Engineer

Undergraduate Research Assistant

Software Development Engineer

Software Development Intern

Carnegie Mellon University

Birla Institute of Technology and Science

Recommendations: 0

Marcus P.E.

Mechanical Design Engineer

Santa Clara, California

Mechanical Design Engineer

rEvolve House Mechanical Engineering Team Leader

Environmental Ethics Fellow

Project Engineering and Management Intern

Global Law and Policy Student Administrative Assistant

Santa Clara University Global Fellow

Santa Clara University

Oak Ridge High School

Recommendations: 0

g****[email protected]

Aaron O'Brien

Senior Hardware Engineer

Santa Clara, California

Senior Hardware Engineer

Senior Systems Application Engineer

Senior Hardware Engineer

Hardware Test Engineer

Hardware Design Engineer

Hardware Engineer

CIA Engineering Student Intern

California State University, Chico

Recommendations: 0