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Vaibhav Tekale

Component Design Engineer

Component Design Engineer at Intel Corporation

San Francisco Bay Area

Section title

Vaibhav Tekale's Email Addresses & Phone Numbers

Vaibhav Tekale's Work Experience

Intel Corporation

Component Design Engineer

October 2014 to Present

San Francisco Bay Area

Calsoft Labs (India) Private Ltd, An Alten Group company

ASIC Design Verification Engineer

March 2013 to October 2014

San Francisco Bay Area

Intel Corporation

Consultant

March 2013 to October 2014

San Francisco Bay Area

Vaibhav Tekale's Education

Vedant (Semiconductor Complex Ltd)

APGD VLSI Design

2006 to 2006

Doctor Babasaheb Ambedkar Technological University

B. Tech Electronics & Tele-communication

2002 to 2006

Dayanand Science College

Higher Secondary School Certificate (12) Science Distinction

2001 to 2002

Vaibhav Tekale's Professional Skills Radar Chart

Based on our findings, Vaibhav Tekale is ...

Strong sense of self
Self-sufficient
Quiet

What's on Vaibhav Tekale's mind?

Based on our findings, Vaibhav Tekale is ...

56% Left Brained
44% Right Brained

Vaibhav Tekale's Estimated Salary Range

About Vaibhav Tekale's Current Company

Intel Corporation

Verification IP expertise.

Frequently Asked Questions about Vaibhav Tekale

What company does Vaibhav Tekale work for?

Vaibhav Tekale works for Intel Corporation


What is Vaibhav Tekale's role at Intel Corporation?

Vaibhav Tekale is Component Design Engineer


What is Vaibhav Tekale's personal email address?

Vaibhav Tekale's personal email address is t****[email protected]


What is Vaibhav Tekale's business email address?

Vaibhav Tekale's business email addresses are not available


What is Vaibhav Tekale's Phone Number?

Vaibhav Tekale's phone (**) *** *** 106


What industry does Vaibhav Tekale work in?

Vaibhav Tekale works in the Semiconductors industry.


About Vaibhav Tekale

📖 Summary

ASIC/FPGA/SoC Verification Engineer with 9 years of experience. Expertise in SystemVerilog, UVM, OVM, VMM. CDV (Coverage Driven Verification) methodology using SystemC as an interface between C++ and verilog. Well versed in UVM, OVM, VMM, RVM Methodology, SystemVerilog, Open Vera HVL. Interested in developing Verification Environment using SystemVerilog, Open Vera. Specialties: Verilog, SystemVerilog, Open Vera, SystemVerilog Assertions, Coverage Analysis, Perl, Bash, UVM, OVM, VMM, RVMComponent Design Engineer @ Verification IP expertise. From October 2014 to Present (1 year 3 months) San Francisco Bay AreaASIC Design Verification Engineer @ Responsible for the verification of the 3D Graphics SoC using UVM. Architect the verification environment and develop the various component like driver, sequencer, monitor, scoreboard in UVM. Develop the verification flow from scratch which includes verification process automation. Define the coverage point and write the functional coverage, assertion. From March 2013 to October 2014 (1 year 8 months) San Francisco Bay AreaConsultant @ Responsible for cluster level and full chip level verification of Complex 3-D Graphics SoC. Architect the cluster level and full chip level Verification Environment. Define the testplan for cluster and full chip RTL. Define the coverage metrics (Coverpoints and Assertions) for cluster and full chip. Develop the various component like driver, sequencer, monitor, scoreboard/reference model in UVM. From March 2013 to October 2014 (1 year 8 months) San Francisco Bay AreaSenior Engineer @ Working on the block level and sub-system level verification of network switches and adaptor. Expertise in OVM, SV, SVA, Verilog. Responsible for the Verification Architecture of the block level and subsystem level, development of the Basic Verification Environment Flow (Includes transaction, configuration, etc), development of the critical modules like reference model, drivers. From November 2010 to February 2013 (2 years 4 months) Pune Area, IndiaMember Of Technical Staff @ 1) Developed Verification Environment Components, testcases, testbenches, verification features. 2) Reviewed of testcases, testbenches, verification features. 3) Code and Functional Coverage analysis. 4) Writing assertions and coverpoints in Systemverilog. 5) Verification Architecture Discussion. From December 2009 to November 2010 (1 year) Ahmedabad Area, IndiaVerification Consultant @ Responsible for verification of IO block of SoC. From April 2010 to June 2010 (3 months) Chennai Area, IndiaASIC Verification Engineer @ 1) Developed Verification Environment Components, testcases, testbenches, verification features. 2) Reviewed of testcases, testbenches, verification features. 3) Code and Functional Coverage analysis. 4) Writing assertions and coverpoints in Systemverilog. 5) Verification Architecture Discussion. From February 2007 to December 2009 (2 years 11 months) Ahmedabad Area, IndiaAPGD, VLSI Design @ Vedant (Semiconductor Complex Ltd) From 2006 to 2006 B. Tech, Electronics & Tele-communication @ Doctor Babasaheb Ambedkar Technological University From 2002 to 2006 Higher Secondary School Certificate (12), Science, Distinction @ Dayanand Science College From 2001 to 2002 Secondary School Certificate (10), General, Distinction @ Shri Shamrao Patil School From 1997 to 2000 Lokmanya Tilak Primary School From 1990 to 1997 Vaibhav Tekale is skilled in: Verilog, SystemVerilog, SVA, Open Vera, Coverage Analysis, Perl, Bash, OVM, VMM, Ethernet, Fibre Channel, USB-2.0, RVM, SoC, Functional Verification, ModelSim


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In a nutshell

Vaibhav Tekale's Personality Type

Introversion (I), Intuition (N), Thinking (T), Judging (J)

Average Tenure

1 year(s), 7 month(s)

Vaibhav Tekale's Willingness to Change Jobs

Unlikely

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