Vaibhav C.'s Email Addresses & Phone Numbers

Component Design Engineer - Graphics Performance Validation @ Part of the Graphics Architecture team. Responsible for developing tools and capabilities to provide infrastructure to run large workloads in Pre-Silicon environment, tools to effectively able to collect and analyze performance data and being able to debug effectively. Responsible for: • Involved in debugging 3D Performance miscorrelation between Graphics...

Component Design Engineer - Graphics Performance Validation @ Part of the Graphics Architecture team. Responsible for developing tools and capabilities to provide infrastructure to run large workloads in Pre-Silicon environment, tools to effectively able to collect and analyze performance data and being able to debug effectively. Responsible for: • Involved in debugging 3D Performance miscorrelation between Graphics Performance Simulator and RTL (Emulation) • Developed Performance analysis tool using C, C++, FSDB reader API’s, Python for analyzing waveforms captured from emulation/simulation • Develop DPI System Verilog tracker’s for capturing performance data from simulation and Emulation model • Debug and analyze of Performance issue observed by running various standard benchmarks • Work with driver, design team to debug issues seen by running graphics workload (Graphics benchmarks) • Worked on improving health of Graphics Performance simulator by running various game frames and micro benchmarks on the simulator From May 2012 to Present (3 years 8 months) Component Design Engineer - Emulation @ Project involved enabling Pre-Silicon BIOS validation on Hybrid Emulation platform • Involved bring up of Hybrid platform using Software simulator (Synopsys Innovator based Virtual model) and Emulation model • Developed software bridge to connect the Software simulator to Emulation model • Engaged with cross site team to improve debug capabilities for hybrid emulation platform Project involved development of Transactors, DPI based Trackers and Emulation Testbenches for supporting Pre-Si Validation on Emulation • Developed SCE-MI (ZEMI3) based trsansactors for enabling Pre-Si validation • Developed DPI based trackers for effective debug, developed RTL triggers using System Verilog Project involved development, deployment and support for In house emulator for Intel CPU and GPU • Implemented High Speed Tracing Solution, to trace/capture data from the Emulator and dumping it out to fsdb file • Involved in supporting and developing the frontend Verilog RTL compiler using C, C++ • Involved in development of System Verilog Assertion (SVA) backend flow • Extensively supported different customers in resolving tool issues/bugs and help bringing up their Emulation model • Developed optimized (based on # of LUT, FF and BRAM) Synopsys Design Ware equivalent library cells in Verilog for the Emulator developed. From July 2007 to May 2012 (4 years 11 months) Intern @ • Bug fixes for System Verilog frontend in C++ • Developed an automated Regression environment using Perl • Writing System Verilog tests to check for language constructs as per the LRM From December 2005 to July 2006 (8 months) Master’s Degree, Computer Engineering @ The University of Texas at Dallas From 2005 to 2007 Vaibhav C. is skilled in: Verilog, SystemVerilog, Perl, C++, Emulation, Simulations, C, Processors, Computer Architecture, RTL Design, Object Oriented Design, Intel, Python, Debugging, System Verilog, Graphics Hardware, Objective-C, CUDA, MongoDB