ASIC Verification Engineer at Enphase Energy. Master of Science in Electrical Engineering from San Jose State University.

ASIC Verification Intern @ • Verification of Mixed signal ASIC used in micro inverters o Develop verification test plans and simulation environments used to validate mixed signal ASICs. o Develop Verilog and SystemVerilog testcases for verification. o Perform RTL and gate level simulations. o Debug and fix RTL bugs. o Perform code coverage analysis From July 2013 to Present (2 years 4 months) Santa Clara, CATechnical Lead @ LANGUAGES: Java 1.5, J2EE DESIGN: UML (Usecases, Class Diagrams ,Sequence Diagrams) DFL(Data Flow Model), DB Design (Conceptual, Logical and Physical) RDBMS: IBM DB2 9.5 WEB & CLIENT-SERVER TECHNOLOGIES: J2EE (JSP-Servlet/Struts), Spring, HTML, JavaScript, Hibernate, Ajax APPLICATION/WEB SERVERS: Apache Tomcat, JBOSS, Web Application Server OPERATING SYSTEM: Windows xp, TOOLS: Eclipse, Editplus, Data Studio Developer, IBM DB2 Control Center CONFIGRATION MGMT: Team Foundation Server, CVS FUNCTIONAL EXPERIENCE: Insurance From February 2008 to July 2012 (4 years 6 months) Bangalore

Master of Science (MS), Electrical and Electronics Engineering, 3.6 @ San Jose State University From 2012 to 2014 B.E, Electronics and Communication Engineering @ Yellamma Dasappa Institute of Technology affiliated to Visvesvaraya Technological University From 2003 to 2007 PU, PCME @ National College From 2001 to 2003 VET From 1994 to 1998 Shreyas Rajeswari is skilled in: ASIC, RTL design, Simulations, RTL verification, Functional Verification, Formal Verification, Static Timing Analysis, Verilog, SystemVerilog, Perl, C, C++, VHDL, Matlab, Python, Synopsys VCS, Synopsys Design Compiler, Altera Quartus, ModelSim, Xilinx ISE, Digital Filters, Filter Design, Unix, SQL, Linux, MyEclipse, Core Java, Java, J2EE Application...