Principle Member Technical Staff @ Bulldozer and Zen RTL Design of Integer Renaming, Scheduling, Execution and Retire Queue Units. K7/K8 floating point datapath and control RTL design and physical design. Verification experience on datapath and control RTL with customized testbenches with direct and random stimulus. Usage of formal design tools (Verplex and Chrysalis). Countless assertion writing, coverage point writing and guidance, irritator development, and stimulus guidance. From November 1995 to Present (20 years 2 months)

BS, Electrical and Electronics Engineering @ Texas A&M University From 1989 to 1994 Mike Achenbach is skilled in: Verilog, Debugging, RTL Design, Semiconductors, IC, Functional Verification, Processors, VLSI, Static Timing Analysis, Physical Design, Perl, computer arch, X86, Microprocessors, Microarchitecture, Low-power Design, Logic Design