• Technical leader with ability to learn new domains quickly and deliver high-quality products in a fast paced start-up environment. Willing (and keen) to be hands on while building a team. • Transitioned from printing hardware development at a public company to storage hardware development in a startup environment. Delivered complex products rapidly by significantly contributing to design and development of the product while building the team. • Strong ability to hire, mentor and retain engineers. Grew the team from five engineers to 50+ engineers in the last two years. Managed the global development teams across three sites with crisp execution for on-time quality product delivery. • Ability to design to cost targets and work with vendors and stakeholders to achieve cost goals.

VP Engineering @ From September 2015 to Present (4 months) Sr. Director, HW & Platform Engineering @ From July 2013 to September 2015 (2 years 3 months) San Francisco Bay AreaDirector ASIC Design Engineering @ Enterprise SSD Controller development Responsible for developing first generation PCIe Gen3 and SAS-12G SSD from SanDisk. Architected the innovative solutions to fit the low-power and high-performance requirements of the enterprise storage market. From May 2011 to June 2013 (2 years 2 months) Director of ASIC Development @ From January 2011 to May 2011 (5 months) Sr. Manager, ASIC Design & Methodology @ Complex ASIC development experience with expertise in architecture, design, synthesis, timing analysis, verification, integration, vendor management, post silicon debugging and project management. Seven first time silicon success on complex multimillion gate ASIC in the last 10 years. Managed and led cross-functional teams from concept to high volume production of complex ASIC in traditional ASIC flow. Developed & employed methodologies for the ASIC/FPGA to drive high quality results. Proven track-record of high quality results on a very tight schedule. Hands on experience for all aspects of chip development process with proficiency in front end design tools and methodologies. From March 2008 to January 2011 (2 years 11 months) Manager, ASIC Design & Methodology @ From December 2000 to February 2008 (7 years 3 months) Member of Technical Staff @ From March 2000 to December 2000 (10 months) Design Engineer @ From April 1997 to March 2000 (3 years) Design Engineer @ From 1997 to 2000 (3 years)

B.Tech, EE @ Indian Institute of TechnologyB.Tech, EE @ Indian Institute of Technology, Kanpur Manoj Agarwal is skilled in: Debugging, ASIC, Static Timing Analysis, Cross-functional Team Leadership, Engineering, FPGA, RTL design, PCIe, SystemVerilog, Project Management, Low-power Design, SoC, Silicon, EDA, Verilog, Semiconductors, VLSI