• Logic Design Engineer at SanDisk Corp. • Education: MSEE at UCLA (Graduated Winter 2013) • Skills: RTL, Prime Time, Verilog, VHDL, Linux, C++, FPGA, MATLAB, Python, Perl

Design Engineer II @ Working under Logic Design Team RTL Design Direct Vector Verification Prime Time Check ECO (Engineering Change Order) From January 2014 to Present (2 years) milpitas, californiaGraduate Research Assistant @ • Design signal processing unit Utilizing Xilinx Virtex 6 Chip • Solve time synchronization problem for high speed system From October 2012 to December 2013 (1 year 3 months) Intern Digital Design Engineer @ Summer internship as Digital Design Engineer From June 2013 to September 2013 (4 months) Greater San Diego AreaIntern Logic Design Engineer @ • Optimized existing functional block based on microarchitecture specification • Programed gate-level circuits into RTL level using VHDL and LEC-check consistency • Synthesized VHDL codes into circuits using Design Compiler From June 2012 to September 2012 (4 months) Intern DRAM Test Engineer @ • Developed programs to enable engineers target desired array space in DRAM chips • Designed test mode combinations and experiments to improve test flow efficiency • Standardized test pattern names to help engineers compare different DRAM products From May 2011 to September 2011 (5 months)

Master of Science (MS), Electrical and Electronics Engineering @ University of California, Los Angeles From 2012 to 2013 Bachelor of Science (BS), Electrical and Electronics Engineering @ University of Washington From 2008 to 2012 Jeff Chen is skilled in: Pspice, Verilog, Matlab, Cadence Virtuoso, VLSI, FPGA, C++, Linux, Python, Signal Processing, Embedded Systems, Perl, Java, C, PSpice