Front End design. Synthesis and STA expert; timing closure of 12 IC tape outs. Verilog/SystemVerilog/VHDL block level coding for ASIC & FPGA. Specialties:Expert with Synopsys Design-Compiler & Primetime. Xilinx embedded development with XPS, EDK, SDK, Chipscope, Virtex 5 and Virtex 6 GTX SERDES. Altera FPGA with Quartus, SignalTap, Stratix

Engineer @ From October 2014 to Present (1 year 1 month) ASIC Engineer @ From June 2013 to October 2014 (1 year 5 months) ASIC Consultant @ From October 2011 to June 2013 (1 year 9 months) Greater San Diego AreaPrototype Engineer @ Responsible for prototyping the DigRF design (PHY and MIPI standard compliant) in bringing up company's first LTE system. From February 2011 to October 2011 (9 months) Principal Engineer @ SystemVerilog & FPGA verification From February 2009 to February 2011 (2 years 1 month) Sr. ASIC Designer @ Synthesis, timing closure, Ikos emulation resulting in 4 tapeouts. Low power design methodologies. From February 2005 to January 2009 (4 years) ASIC Consultant @ RTL coding, verification, synthesis, STA. Commercially released ASIC. From January 2003 to February 2005 (2 years 2 months) ASIC Consultant @ All aspects of IC design From February 1998 to December 2002 (4 years 11 months) CAD AE @ Synopsys CAD tools AE From May 1995 to January 1998 (2 years 9 months) Sr. ASIC Engineer @ Tapeout of HDSL Framer ASIC. From 1994 to 1995 (1 year) ASIC Engineer @ From 1986 to 1994 (8 years)

MSEE @ Southern Methodist University From 1986 to 1988 BS, EE @ University of Florida From 1981 to 1985 Gilbert Nguyen is skilled in: Chipscope, ASIC, Verilog, SDK, SystemVerilog, FPGA, Timing Closure, Xilinx, Embedded Systems, Processors, Static Timing Analysis, Logic Synthesis, Primetime, EDA, RTL coding, LTE, Integrated Circuit..., Altera, Debugging, Low-power Design, Emulation, IC, Quartus