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Chris Rayner

Electrical Engineer, Office of the CTO/R&D group

Sr. Hardware / Systems Engineer - OUTFRONT Media

Andover, Massachusetts

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Chris Rayner's Email Addresses & Phone Numbers

Chris Rayner's Work Experience

APC by Schneider Electric

Electrical Engineer, Office of the CTO/R&D group

April 2011 to Present

Redwood Technologies LLC

Embedded Firmware Engineer

January 2010 to March 2011


Hardware Support Engineer (contract)

April 2004 to December 2006

Chris Rayner's Education

University of Massachusetts at Lowell


2011 to 2017

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Chris Rayner's Estimated Salary Range

About Chris Rayner's Current Company

APC by Schneider Electric

Enterprise management systems development. Support of touchscreen LCD displays for line of power converters. Development of ZigBee mesh end nodes/coordinators/routers for line of remote environmental monitoring sensors. Development of small solar charge solution for zero-downtime mesh networking. Initial HW design / debug / firmware integration.

Frequently Asked Questions about Chris Rayner

What company does Chris Rayner work for?

Chris Rayner works for APC by Schneider Electric

What is Chris Rayner's role at APC by Schneider Electric?

Chris Rayner is Electrical Engineer, Office of the CTO/R&D group

What is Chris Rayner's personal email address?

Chris Rayner's personal email address is c****[email protected]

What is Chris Rayner's business email address?

Chris Rayner's business email addresses are not available

What is Chris Rayner's Phone Number?

Chris Rayner's phone (413) ***-*186

What industry does Chris Rayner work in?

Chris Rayner works in the Computer Hardware industry.

About Chris Rayner

馃摉 Summary

Experienced Computer Hardware Engineering Consultant, development of complex embedded systems, diagnostic frameworks, FPGA and validation code for a myriad of high tech companies including Lucent, Fujitsu, Avid, NewbridgeElectrical Engineer, Office of the CTO/R&D group @ Enterprise management systems development. Support of touchscreen LCD displays for line of power converters. Development of ZigBee mesh end nodes/coordinators/routers for line of remote environmental monitoring sensors. Development of small solar charge solution for zero-downtime mesh networking. Initial HW design / debug / firmware integration. From April 2011 to Present (4 years 9 months) Embedded Firmware Engineer @ Developed firmware for FPGA based queue management engine with 1Gb ethernet front end feeding 8 print head queues. From January 2010 to March 2011 (1 year 3 months) Hardware Support Engineer (contract) @ 6 mo contract extended to 32 months Supported ASIC emulation cards and development boards for line of H264 decoder chips. Design/layout/bring up of BluRay DVD reference design that eventually became basis for LG, and Samsung commercial products. From April 2004 to December 2006 (2 years 9 months) Principle Hardware Engineer @ 路 Architectural development and implementation of 4-port STS-12 cross connect card for Chromatis 4500 optical switch, providing trunk grooming at the VT1.5 sub rate. 路 Architectural development and hardware lead for multi-function circuit emulation line card designed to work as a front end to a PON solution (i.e. Verizon FiOS equivalent). 路 Design was capable of performing aggregation/performance monitoring on 56 (42) T1 (E1) line interfaces, 2 structured/unstructured DS3 or STS1 interfaces, expandable to 4 with additional daughter card. Architecture was fully hot-swappable, and fault tolerant with automatic reconfiguration/repartitioning.. 路 Designed hardware, wrote FPGA code in verilog, developed embedded diagnostic framework in C running under VXWorks. Brought-up design in lab (typical analyzer/emulator based debug cycle), verified and debugged to full functionality. 路 Wrote hardware specification, developed schedules and needed documentation. Led group of 4 engineers and 2 technicians. 路 Interfaced with PMC as an early integrator of PMC/Sierra's TEMUX chip; finding/debugging chip driver issues along the way. Delivered production ready design on time within budget in 1 re-spin cycle (motherboard, daughter card, 1-dual board I/O module, 1 3-board I/O module). From July 1999 to September 2001 (2 years 3 months) Hardware Engineering Consultant @ 路 Implemented adaptive rate clock recovery FPGA for 8-port T1/E1 circuit emulation card. 路 Performed debug and re-spin of 10/100 Ethernet line card due to improper 2.5V plane layout and bugs in auto-negotiation cycle. From January 1999 to July 1999 (7 months) Consulting Validation Engineer @ 路 Design and implementation of ASIC validation environment in C++ and VHDL centered around proprietary socked based simulation interface. 路 Developed behavioral simulation (dataflow) model for streaming JPEG color correction engine as a standalone entity allowing test development to occur prior to delivery of structural code from the design group. 路 Developed targeted tests and a random testing environment. 路 Interfaced with designers to verify bugs, developed schedules and performed resource allocation. From April 1998 to January 1999 (10 months) Senior Hardware Engineer @ 路 Architectural analysis and redesign of 6-port T1/E1 frame relay line card for Nexen8000 ATM switch. 路 Performed a full board level Verilog simulation on 8-microprocessor system (including 6 Motorola 68360 QUICC devices) using LMC simulation models. 路 Wrote QUICC diagnostic code in C for debug in simulation. Resulting redesign had 1 miswire on a board with 5500+ nets. 路 Redesign of common verilog PCI interface FPGA common across the Nexen8000 line cards resulting in a more portable, smaller, faster implementation. From April 1997 to April 1998 (1 year 1 month) Senior Hardware Engineer @ Added input buffers to un-buffered ATM OC3 line card - implemented in Lucent FPGA's 60K gate schematic based design. Developed i860 based processor module for Duckling ATM switch (joint venture w/Xerox PARC). Performed architectural analysis on several system topologies via discreet event simulation written in C++ resulting in improved throughput for several legacy bus architectures. From July 1992 to 1997 (5 years) Eng Tech @ Modified open source "C" based packet driver software into suite of engineering system test software for line of modular stackable managed ethernet hubs. Drove manufacturing test efforts, provided DFM input, and initial system debug. From August 1991 to July 1992 (1 year) Research Technician @ Developed a wide band high powered video amplifier for a line of DARPA funded spatial light modulators used in a missile guidance system test bench. From 1991 to 1991 (less than a year) Test Engineer @ Wrote embedded systems diagnostics to aid in technician component level debug for series of disk drive and communications controllers. Trained 2nd shift technician staff resulting in 600% improvement in throughput. Brought up new test fixtures, characterized ASIC failures in custom silicon using embedded knowledge and black box test strategies pre-decavitation. From 1986 to 1991 (5 years) MSEE @ University of Massachusetts at Lowell From 2011 to 2017 Chris Rayner is skilled in: Embedded Systems, Firmware, FPGA, Hardware Architecture, VHDL, PCB design, Verilog, ASIC, Embedded Software, USB, C, Altera, ATM networks, IMA, PowerQUICC

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In a nutshell

Chris Rayner's Personality Type

Introversion (I), Sensing (S), Thinking (T), Perceiving (P)

Average Tenure

2 year(s), 3 month(s)

Chris Rayner's Willingness to Change Jobs



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