More than 15 years of digital design and validation of complex ASIC and FPGA commercial and military communications products. Extensive experience in mapping algorithms and specifications to hardware architectures and developing test plans, test benches and verification environments. Highly motivated with broad experience and interest in solving complex problems. Specialties: Hardware: Xilinx, Altera, Actel, ASIC, ARM Software: Modelsim, Synopsys, Simplicity, Cadence, Matlab Languages: Verilog, VHDL, System Verilog, SVA, Perl, Python, TCL, C/C++ Standards: ARM, AXI, AHB, Bluetooth, 802.11a, CDMA, 802.16e

Lead FPGA Engineer @ Designed Altera soft processor FPGA for proprietary FFT based DSP algorithm and MAC functionality. Product included 500MHz ADC, NIOS, DDR3 Flash, Ethernet, SPI and DSP. Developed C and Verilog code for design and simulation. Bit matched Matlab and Verilog code for DSP. Integrated NOIS and DSP subsystems and validated built design in the lab. (contract engineer) From March 2013 to October 2014 (1 year 8 months) Carlsbad CALead FPGA Engineer @ Developed Xilinx FPGA, Altera FPGA and ARM based Video and Data over IP products utilizing the DVB, RTP and TS standards. Completed entire MAC layer design from architecture to simulation and verification to integration with firmware and validation in the lab. Created VHDL and Verilog RTL and testbench code and implemented IP for GTX, DDR3, AXI-Stream Ethernet MAC, Frame Buffer, and (De)Encapsulate blocks From July 2011 to February 2013 (1 year 8 months) Irvine CASenior ASIC Engineer @ (contract engineer) Verification Engineer for ARM and AXI based System on Chip 45nm multi-million gate ASIC. Top level verification using C programs, System Verilog, System Verilog Assertion and TCL scripts. Developed new verification methodology for AXI-lite peripheral block using SVAs From August 2010 to June 2011 (11 months) Irvine CASenior FPGA Engineer @ (contract engineer) From March 2010 to June 2010 (4 months) Encinitas CASenior ASIC/FPGA Engineer @ (contract engineer) Hardware architecture and verification methodology evaluation and design improvements. Co-Verification using Virtex5 and ARM7 ChipIt Platform including Xilinx synthesis and Modelsim simulation and VHDL/Verilog coding. Design of ARM7 Bus Functional Model. From June 2009 to December 2009 (7 months) Senior ASIC Engineer @ (contract engineer) Senior Verification Engineer for three 45nm 30million+ ASICs. Executed advanced verification including: System Verilog Assertions, Vera, VHDL and regression testing. Additonally responsible for block level clock and power control verification. From October 2006 to April 2009 (2 years 7 months) Project Engineer @ (San Diego Research Center acquired by Argon ST) Hardware architected, implemented and tested multiple wireless modems. Implementation accomplished in Xilinx FPGAs. These designs were used for government research and development demonstrations as well as small scale production products. From 2003 to 2006 (3 years) Senior Staff ASIC Engineer @ (Innocomm Wireless acquired by National Semiconductor) Lead Digital ASIC Engineer for the Bluetooth project. Participated in three ASIC tapeouts of the LMX5250 Bluetooth radio chip from rtl changes through validation of silicon in the lab. From 2000 to 2002 (2 years) ASIC Engineer @ (contract engineer) Consultant position involving design and verification of two camera ASICs. Designed ARM AHB to Agilent Bus bridge logic. Verified the entire design by writing C tests for use with the co-verification environment (C model and Verilog rtl). From 1999 to 2000 (1 year) Senior Engineer @ (ComStream acquired by Raydyn acquired by Comtech) Implemented RTL VHDL code for modulator and demodulator functions. Simulated, synthesized and placed/routed the designs into two Altera FPGAs. From 1998 to 1999 (1 year) Member of Technical Staff @ FPGA and PCB design and verification engineer for modem and camera projects. Developed Altera and Actel FPGAs. From 1995 to 1998 (3 years) Engineer @ Designed and developed betting terminal products for the horse race industry from breadboard to FCC testing. Implemented Altera and Lattice programmable logic. From 1993 to 1995 (2 years)

MSEE, Communications @ San Diego State University-California State University From 1991 to 1993 BSEE @ University of Massachusetts, Amherst From 1984 to 1989