Trevis Lunsford's Email Addresses & Phone Numbers

Contract FPGA Engineer @ Mustang Technology Designed FPGA logic implemented on COTS eval/demo boards for radar related DoD proof of concept. Obtained security clearance. Resigned after the sale of our Texas house in order to return to Charlotte after 18 years in DFW. From March 2013 to May 2013 (3 months) Plano, TXFPGA Engineer @ ADVA Optical...

Contract FPGA Engineer @ Mustang Technology Designed FPGA logic implemented on COTS eval/demo boards for radar related DoD proof of concept. Obtained security clearance. Resigned after the sale of our Texas house in order to return to Charlotte after 18 years in DFW. From March 2013 to May 2013 (3 months) Plano, TXFPGA Engineer @ ADVA Optical Networking My responsibilities were designing module testbenches and testcases and contributing to full chip tests as well using System Verilog and UVM verification. From January 2009 to June 2010 (1 year 6 months) Senior FPGA Design Engineer @ Ceterus Networks My responsibilities were to design Xilinx or Altera FPGA and CPLD logic to run on proprietary hardware for the telecommunications industry. I also wrote testbenches and testcases to simulate and verify the designs. Participated in lab testing the products with bench testers, oscilloscopes, logic analyzers and Xilinx ChipScope and Altera SignalTap. From March 2002 to December 2008 (6 years 10 months) Applications Engineer @ Cicada Semiconductor My responsibility was to design FPGA logic to be used on a development board for the express purpose of testing an ASIC designed by other team members. From October 2001 to March 2002 (6 months) Austin, TXSenior Engineer II - FPGA @ Overture Networks My responsibilities were designing RTL code to implement Ethernet and SONET/LCAS protocols in FPGAs and designing bus functional models, testbenches and testcases to simulate and verify FPGA designs. Verilog and System Verilog was mostly used along with some UVM and also some VHDL. From July 2010 to November 2012 (2 years 5 months) ASIC Engineer @ Metera Networks Some responsibilities were: Contribute to writing detailed chip architecture and specification documents using Frame Maker. Write RTL code in Verilog to implement the specifications into the FPGA. Simulate and verify the FPGA using NCSim. From 2000 to 2001 (1 year) Engineer @ NCR Some responsibilities were to write 8051 assembler code for magnetic stripe readers and to contribute to design and testing of cash registers. Assisted with EMI/RFI testing of cash registers and incorporation of resultant design modifications. From March 1970 to February 1983 (13 years) Clemson, SC (2 yr) and Cambridge, OH (11 yr)Senior Electronics Engineer @ Aramark Healthcare Technologies Responsibilities included researching design details of OEM medical imaging diagnostic equipment to discover the faulty components and develop repair & test procedures. Some of these circuits were centered on FPGAs, CPLDs, DSPs, CPUs and memory. From August 2013 to December 2014 (1 year 5 months) Charlotte, NCPrincipal Engineer @ BancTec Responsibilities were to design electronic hardware utilizing microprocessors, memories, TTL & CMOS logic chips, FPGAs and CPLDs. These designs were for a myriad of purposes including optical character recognition, ink jets, E13B printer stepper motor control and microfilming. Tool usage included OrCad for shematic capture, PADS for PCB artwork, 8085 & 8051 assemblers and C compilers, Xilinx ISE along with Palasm type tools. From February 1983 to October 2000 (17 years 9 months) Irving, TX and Charlotte, NC