Tim Balbekov’s Email & Phone

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Tim Balbekov

Silicon Design Engineer II @ Microsoft

Tim Balbekov Contact Details

Seattle, Washington
Silicon Design Engineer II @ Microsoft
Hardware Engineering Intern @ Microsoft
Analytics and Metrology Intern @ Osram Opto Semiconductors

Silicon Design Engineer @ Designed low-latency SoC memory controller IP blocks in Verilog. Verified existing memory control blocks in SystemVerilog. Developed an accelerated FPGA hardware/software co-simulation environment. From March 2014 to Present (1 year 10 months) Hardware Engineering Intern @ Designed and implemented bus hardware logic for FPGA simulation in Verilog. Verified existing hardware accelerators in SystemVerilog. 

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