I am a highly motivated, extremely productive and efficient R&D engineer. I am a full-time senior R&D engineer at NOV Downhole in Conroe, TX. I am looking for possible contract work in addition to my work at Downhole. Specialties: Skill Years used Last used Verilog >10 2015 VHDL >10 2015 Matlab >10 2015 C >10 2015 C++ 5 2015 ASIC >10 2014 FPGA >10 2015 Shell >10 2015 Tcl >10 2015 Perl 3 2015 Networking 7 2015 Research >10 2015

Sr. R&D ECE @ Architect of custom VHDL digital hardware for next generation Downhole electronics. From February 2013 to Present (2 years 11 months) IEEE Senior R&D Electrical Engineer, Technical Team Lead Verilog Group @ Design+Verification of high temperature FPGA/ASIC for NOV-IntelliServ high speed downhole network. RF system modeling for NOV-IntelliServ high speed downhole network using Verilog, PLI, SPICE, Matlab, COMSOL Multiphysics. From July 2007 to February 2013 (5 years 8 months) Senior Design Engineer @ From 1997 to 2002 (5 years)

Master's Degree, Computer Engineering, 3.8/4.0 GPA @ Louisiana State University From 2002 to 2007 Master's Degree, Electrical and Electronics Engineering, 3.9/4.0 GPA @ UNCC From 1995 to 1997 Stephen Bishop is skilled in: FPGA, ASIC, Research, Verilog, Xilinx, RTL design, Altera, SoC, ModelSim, DSP, EDA, Digital Design, Analog, VLSI, DFT