• More than 15 years working experience in designing, validation and debugging PCB hardware in embedded, data acquisition, communication, wireless , Enterprise Storage systems. • More than 10 years signal integrity and power integrity experience in Pre-silicon/Post-silicon and Pre-PCB/Post-PCB simulations and AC timing analysis, correlation of digital high speed interfaces and power distribution systems. • 9 years validation and debugging experience using Logic analyzer, Digital O-scope, Spectrum Analyzer, Digital Serial Analyzer TDR, VNA, BERT. • Proficient in high-speed digital design methodology, signal integrity and power delivery simulation and timing analysis, FPGA/microprocessor integrity, FPGA coding, schematic capture, PCB layout and routing (mixed-signal and RF high- speed PCB stack-up multilayer), hardware bring-up and debug, and documentation for production. • Extensive working experience with Special tools: Cadence Allegro, SPECTRAQuest, Orcad; Agilent ADS; Mentor Graphics PADS, ; Ansoft HFSS, Siwave, Ansoft Designer; Iconnect; statistics tool Jump and product data management Agile and Profile. • Extensive hands-on programming experience with C, Perl, Tcl, Matlab, VHDL in Unix and Windows. • Extensive working experience in digital high speed interfaces and PDN systems such as DDR3/DDR2/DDR SDRAM, Toggle Mode NAND Flash, Serdes serial links, FPGA transceivers, 10GbE(XAUI), SAS, SATA and PCIe. Extensive working experience on HSPICE transistor level model, IBIS model, IBM-AMI model, IBIS+ model.

Sr. Staff Hardware Engineer (Signal/Power Integrity) @ My responsibilities include the pre and post PCB layout signal and power integrity analysis, simulation, AC timing analysis, verification and validation for the Enterprise Solid State Drive with Synopsys HSPICE, Agilent ADS and Momentum, Ansoft HFSS, HyperLynx GHZ SI/PI. The interfaces include Toggle Mode 2D/ 3D NAND, DDR3 SDRAM, 12Gbps SAS, SATA and PCIe. From June 2014 to Present (1 year 5 months) Sr. Hardware Engineer( Signal /Power Integrity) @ My responsibilities include the pre and post PCB layout signal and power integrity analysis, simulation, AC timing analysis, verification and validation for the high speed systems with 3D Solver HFSS, HyperLynx GHZ SI/PI, which includes DDR3/DDR2/DDR memory interfaces, 10.3125Gbps SFP+ , 6.25Gbps serial link backplane, 10GbE(4x3.125Gbps XAUI), over 3.125Gbs and 6.25Gbps Serdes, 5Gbps PCIe etc. The main duties include: • Pre-layout high speed signal integrity and power delivery simulation and timing analysis including stackup design, PCB materials (FR4/embedded capacitor materials) analysis, channel design ( BGA channel breakout, routing topology, signal via , DC blocking capacitors, interface connectors), AC decoupling analysis, power plane and IR drop analysis etc.. • Delivering the high speed PCB routing guidelines to the PCB internal teams and PCB outsource vendor. • Post-layout high speed signals signal integrity and power delivery simulations and PCB reviews. • Characterization the high speed signals at time/frequency domains and correlation validation. • High speed channel simulations (IBIS-AMI) to characterize pre-emphasis and equalizer settings. • System high speed signals validation and debugs. From 2008 to June 2014 (6 years) Tempe, AZAnalog Engineer ( Signal/Power Integrity) ( acquisition from Intel) @ My responsibilities include the pre-silicon and post-silicon signal integrity/power delivery analysis, verification and validation for various interfaces such as DDR,DDR2 USB, high speed MIPI, OneNAND, etc. The main duties are: • Signal integrity simulation and AC timing analysis with Hspice and SPECTRAQuest. • IBIS and EBD model generation from IO netlists and correlation( transistor level I/O model and validation). • Leveraging various data and DOE (JUMP) methodology to optimize solutions for interfaces. • Optimizing the interconnect design from package and PCB routing guides, driver strength and slew rate settings, decoupling schemes. Delivering design guides for customers and internal teams. • Post-Silicon SI/PD validation and debug (from signal quality and AC timing views cross PVT corners). From 2006 to 2007 (1 year) Chandler, AZAnalog Engineer (Signal /Power Integrity) @ My responsibilities include the pre-silicon and post-silicon signal integrity/power delivery analysis, verification and validation for DDR, USB, NAND, High speed MIPI, etc. interfaces. The main duties are: • Signal integrity simulation and AC timing analysis with Hspice/SPECTRAQuest. • IBIS and EBD model generation from IO netlists and correlation( transistor level I/O model and validation). • Leveraging various data and DOE methodology (JUMP) to optimize solutions for interfaces. • Optimizing the complete path from silicon I/O pad, package and interconnects. Delivering the design guides. • Post-Silicon SI/PD validation and debug (from signal quality and AC timing views cross PVT corners). From 2005 to 2006 (1 year) Chandler, AZHardware Engineer @ My responsibilities include Ethernet PHY Radio Card, MiniPCI Card, 10/100 Base Ethernet lighting protection, PCI-to-PCI Bridge Card for Wireless LAN based on 802.11 & 802.3 standards. The main duties are:: • Signal integrity simulation and timing analysis of pre- and post-PCB layout. • Deriving physical constraints, termination schemes and optimized topologies and PCB stackups. • PCB layout and routing (mix-signal and RF PCB layout, high-speed PCB stack-up multilayer), design releases and documentation. Debugged the prototype. From 2003 to 2005 (2 years) Ontario, Canada

MSc., System Science, Electrical engineering @ University of OttawaBachelor's Engineering, Electrical Engineering @ Tianjin University Sarah Shen is skilled in: Semiconductors, ASIC, SoC, IC, Embedded Systems, Verilog, Debugging, Mixed Signal, Analog, FPGA, Embedded Software, RTL design, Signal Integrity, Power integrity, High Speed Digital, Hardware, VHDL