Hands on experience with RF/Analog, Digital Product Characterization using ATE( UFLEX) & LabView bench on TX/RX, PLL,Power Management blocks & Reliability Qualification. Proficient with DAC/ADC, signal integrity,Gate level verification & IP integration.Solid understanding with Digital, RF Analog, Mixed signal circuit analysis/modulation techniques & wafer fabrication fundamentals. Tools: Quartus, Eclipse, Cadence Virtuoso/Spectre, Synopsys VCS (Design Compiler, Primetime, IC Compiler), Modelsim, Datapower, Labview, Teradyne IGXL on UFLEX Prober and SEDANA.

RF/Analog Characterization/Application Engineer @ • Full Product Characterization Qualification/Debug/Bringup of the 60Ghz RF WiGig product for Data Reviews over Voltage, Temperature ,Frequency and DoE wafers TX Block : EVM ,SNR, EIRP ,Phase Noise, Gain tests RX Block: RX Sensitivity, Rx Range, Noise Figure tests VCO/PLL Block: PLL Characterization, Spot Noise measurement,XTAL Characterization. Power management modules: LDO Line/Load Regulation, Power /Current measurement. Propagation Loss Measurement: RF Signal Scattering measurement calibration • Designed and developed Post Silicon reliability qualification test plans such as HTOL/ESD/LU and lead quality test board designs/debug. • Defined test compliance matrix, provided engineering analysis & simulations to validate new designs. Spearheaded development, bring up & characterization activities, took requirements from Design, Operations, Systems, Hardware/Firmware teams to meet customer demands. • Worked closely with contract manufacturers by giving requirements and fixing issues with test board prototyping in Taiwan and China. • Defined requirements for production test platform. Concept development & verification of blocks including RF, Digital & Analog modules. • Setup live product demos at major trade shows to showcase & attract new potential customers ,overlooked procurement of equipment and components by coordinating with suppliers. • Researched and collected industry trends, new marketing requirements, customer feedback, market problems, competitor information that impacted design and global product plans. From October 2014 to Present (1 year 3 months) Greater San Diego AreaRF/Analog Product Development Engineer @ • Characterization/bring up of LTE, GSM,UMTS/WCDMA Transceivers, PA’s & NFC devices for data reviews on bench/ATE. Correlated bench tests such as Gain, NF, SNR, IP3, IDDq, ACPR, EVM, Linearity, LDO Line/Load regulation, PLL VCO Phase Noise measurement. • Automated/developed looping test scripts using Lab View panels to quicken data collection over process voltage and temperature. • Contact for off shore teams in TSMC/GF for wafer BIN sorting, Cp Cpk yield analysis, foundry matching, GR&R, site to site correlation. • Debugged RMA’s by root cause analysis & fault isolation on PLL’s, ADC/DAC’s, LNA’s SAW/BAW filters, TX/RX and PMM blocks. • Verification & bring up of HTOL/ESD/Latch Up action plan, stress conditions, bring up of ATE ATPG/MBIST test patterns. • Published findings from FMEA (Functional, Design & Process) using Failure Analysis & Thermal Emissions to lower chip failure rate. • Calibrated 40nm chipset devices on DUT cards for Impedance/Resonance matching using Smith Charts, Network Analyzer & Load pull matching. From December 2012 to October 2014 (1 year 11 months) Greater San Diego AreaHardware Test Engineer @ • Assembled power supplies, heat sinks, LCD’s, Mezzanine card, RAM’s to build Packet brokers , aggregators, switches & VGAN testers. • Conducted tests & evaluation on Network Packet Brokers 1GE/10GE/40GE/100GE over copper and optical fiber interfaces. • Implemented test plans defining goals for testing mezzanine cards, LCD interfaces and I/O ports. Programmed CPLD’s & FPGA’s to demonstrate system level functionality. Assisted in troubleshooting and debug of PCB’s stability, measured Insertion Loss and Mismatch. From October 2012 to December 2012 (3 months) Systems Test Engineer @ • Developed & implemented compatibility protocols to assess hardware device reliability & functionality based on PC’s operating condition. • Automated updates remotely using GFI LAN GUARD. Configured & fixed issues regarding TCP/IP, DNS, DHCP, WINS, Gateway VPN. Deployed a Symantec Ghost Cast server, pushed/pulled, standard/custom images remotely over 500 SF State owned systems. • Implemented a Windows and Linux based servers to integrate and validate system design & administrative authentication. Servers housed web based “Library inventory” & “Library e-ticketing” system running on PHP & MySQL as frontend & backend design respectively. From May 2011 to May 2012 (1 year 1 month) Undergraduate Intern/Hardware Design Intern @ Low Dropout Voltage Regulator for battery driven applications : Optimized architecture design using Band Gap Reference generator model to supply different voltages with variation in temp (-30C to80C) to different sub blocks. Design predicted increased battery life up to 30%. Tools used: Cadence Spectre, Cadence Virtuoso, TSMC 180nm From January 2010 to June 2010 (6 months)

Master's degree, Business Administration, Management and Operations @ Coleman University From 2015 to 2017 Master's degree, Electrical Engineering /RF Analog /Embedded Systems @ San Francisco State University From 2010 to 2012 Bachelors in Electronics/Telecommunication Engg, Embedded Systems, V.L.S.I, Logic Design, Analog/Digital Electronics, Digital Signal Processing @ Visvesvaraya Technological University From 2006 to 2010 Rajath Narasimha is skilled in: RF Circuits, Product Development, Device Characterization, Analog Circuit Design, Verilog, Linux, VHDL, FPGA, ASIC, Embedded C, Embedded Systems, System Verification, Hardware Testing, SoC, DFT