Rajath Narasimha’s Email & Phone

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Rajath Narasimha

Lead Diagnostics Engineer - System Verification Group @ Cadence Design Systems

Rajath Narasimha Contact Details

Location:
San Jose, California, United States
Work:
Lead Diagnostics Engineer - System Verification Group @ Cadence Design Systems
RF/Analog Characterization/Application Engineer @ Tensorcom
RF/Analog Product Development Engineer @ Qualcomm
Education:
Master's degree, Business Administration, Management and Operations @ Coleman University
About:

Hands on experience with RF/Analog, Digital Product Characterization using ATE( UFLEX) & LabView bench on TX/RX, PLL,Power Management blocks & Reliability Qualification. Proficient with DAC/ADC, signal integrity,Gate level verification & IP integration.Solid understanding with Digital, RF Analog, Mixed signal circuit analysis/modulation techniques & wafer fabrication fundamentals. Tools: Quartus, Eclipse, Cadence Virtuoso/Spectre, Synopsys VCS (Design Compiler, Primetime, IC 

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