Pallav Singh's Email & Phone - Infineon Technologies

Pallav Singh's Work Experience

Infineon Technologies

Software Engineer - 2

August 2003 to October 2006

Bengaluru Area, India

Cadence Design Systems

SMTS

October 2009 to June 2011

Noida Area, India

Mentor Graphics

SMTS

October 2006 to October 2009

Hyderabad Area, India

Pallav Singh's Education

St. Joseph's Academy, Dehradun

Institute of Engineering and Technology

Bachelor of Technology (B.Tech.), Computer Science

1999 to 2003

About Pallav Singh's Current Company

Infineon Technologies

Worked in the development of Session Initiation Protocol (RFC - 3261) stack, signal compression (SigComp RFC - 3320) and User Agent of SIP stack library. Core responsibility was to implement IETF RFC's in the SIP Signaling Stack (change encoder, decoder, FSM's of transaction layer, transaction unit, and User Agent module, Interaction with RTP protocol (RFC - 1889)...

About Pallav Singh

📖 Summary

Software Engineer - 2 @ Infineon Technologies Worked in the development of Session Initiation Protocol (RFC - 3261) stack, signal compression (SigComp RFC - 3320) and User Agent of SIP stack library. Core responsibility was to implement IETF RFC's in the SIP Signaling Stack (change encoder, decoder, FSM's of transaction layer, transaction unit, and User Agent module, Interaction with RTP protocol (RFC - 1889) stack and application module) w.r.t Call Flow. From August 2003 to October 2006 (3 years 3 months) Bengaluru Area, IndiaSMTS @ Cadence Design Systems Worked on development of dynamic Assertion Based Verification (formal verification) engine for compiler of Hardware async parallel languages (System Verilog LRM - 2003, 2009), NcSim • Generate abstract syntax Tree. • Property and. • Recursive property. • Local variable initialization (per Attempt forked, per Instance, invoked basis). • Pass by reference of variables across multiple Branching operators. From October 2009 to June 2011 (1 year 9 months) Noida Area, IndiaSMTS @ Mentor Graphics • Developed Instruction-Accurate model for ARM Processor (Cortex R4, M3, A8), Thumb and ARM Mode instructions. • Developed ARM CortexR4 PSP (Processor Support Package). The job involved integrating Instruction Set Simulator with Co-Verification kernel, developing AXI, AHB Master (bus protocol) and TCM protocol (memory protocol). From October 2006 to October 2009 (3 years 1 month) Hyderabad Area, IndiaSoftware Engineer @ Microsoft Azure Networking Senior Software Engineer @ Bloomberg LP Feed Infrastructure Team From July 2018 to April 2020 (1 year 10 months) Greater New York City AreaPrincipal Software Engineer @ Cadence Design Systems Worked on development for compiler of Hardware async parallel languages (VHDL), NcSim• Support for signal expression (inside scalar and composite data types) at a port map, whose value changes at run time on clock pulse (VHDL-2008 LRM). From February 2013 to December 2014 (1 year 11 months) Noida Area, IndiaSoftware Engineer - 4 @ Cisco Worked on IOS XR ( distributed operating system), Platform-Infra Team of Cisco. • Concurrent database management which allow service instances (L3 protocols: OSFF, RIP) to re-start gracefully on different node, when load balancer kills them, without effecting registered dependent services.• Virtual route forwarding group support • Virtual NIC Interface attribute Library. From June 2011 to February 2013 (1 year 9 months) Bengaluru Area, IndiaStaff Software Engineer @ FireEye, Inc. • As part of Hyper-visor's platform team worked on implementing Instruction Emulator for Intel assembly, needed during booting different Windows OS over secure Hyper-visor •Worked on HX and MIR application Servers of FireEye, which collect file’s, triages (useful information from agents running on endpoint CPU’s of cluster or Enterprise’s to determine if an endpoint is possibly under security attack or not), and does CPU containment. From December 2014 to June 2018 (3 years 7 months) San Jose, California

Pallav Singh’s Personal Email Address, Business Email, and Phone Number

are curated by ContactOut on this page.

Frequently Asked Questions about Pallav Singh

What company does Pallav Singh work for?

Pallav Singh works for Infineon Technologies

What is Pallav Singh's role at Infineon Technologies?

Pallav Singh is Software Engineer - 2

What is Pallav Singh's personal email address?

Pallav Singh's personal email address is s****[email protected]

What is Pallav Singh's business email address?

Pallav Singh's business email addresses are not available

What is Pallav Singh's Phone Number?

Pallav Singh's phone (212) ***-*374

What industry does Pallav Singh work in?

Pallav Singh works in the Computer Networking industry.

Who are Pallav Singh's colleagues?

Pallav Singh's colleagues are Iat Chan, Diego Ceccarelli, Lingyu Lu, David Stockley, Stefan Petrov, Federica Cremasco, Oliver Callington, Amit Savani, Matthieu Vincke, and Khalil Dayri

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In a nutshell

Pallav Singh's Personality Type

Extraversion (E), Intuition (N), Feeling (F), Judging (J)

Average Tenure

2 year(s), 5 month(s)

Pallav Singh's Willingness to Change Jobs

Unlikely

Likely

Open to opportunity?

There's 90% chance that Pallav Singh is seeking for new opportunities

Pallav Singh