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Mohan Krishnareddy

Applications Architect

Applications Architect at Arteris IP

Sunnyvale, California

Section title

Mohan Krishnareddy's Email Addresses & Phone Numbers

Mohan Krishnareddy's Work Experience

Arteris IP

Applications Architect

Arteris IP

Solutions Architect

San Francisco Bay Area

Wave Computing

Principal SoC Engineer

June 2019 to November 2019

Campbell, California

Mohan Krishnareddy's Education

Visveswaraiah Technological University

Bachelor of Engineering, Electronics & Communications

2003 to 2007

University of Southern California

Master of Science, Electrical Engineering (VLSI Design)

2008 to 2010

Mohan Krishnareddy's Professional Skills Radar Chart

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Calm under pressure

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Based on our findings, Mohan Krishnareddy is ...

56% Left Brained
44% Right Brained

Mohan Krishnareddy's Estimated Salary Range

About Mohan Krishnareddy's Current Company

Arteris IP

Frequently Asked Questions about Mohan Krishnareddy

What company does Mohan Krishnareddy work for?

Mohan Krishnareddy works for Arteris IP

What is Mohan Krishnareddy's role at Arteris IP?

Mohan Krishnareddy is Applications Architect

What is Mohan Krishnareddy's personal email address?

Mohan Krishnareddy's personal email address is m****[email protected]

What is Mohan Krishnareddy's business email address?

Mohan Krishnareddy's business email addresses are not available

What is Mohan Krishnareddy's Phone Number?

Mohan Krishnareddy's phone (213) ***-*309

What industry does Mohan Krishnareddy work in?

Mohan Krishnareddy works in the Computer Hardware industry.

Who are Mohan Krishnareddy's colleagues?

Mohan Krishnareddy's colleagues are Kevin Lam, Zohreh Azizi, Jolene Bishop, Kay Jimissa, Rufino III, Denissa Venturanza, Rohini Jayaram, Jon Wang, Don Smith, and Kam-Wing Li

About Mohan Krishnareddy

đź“– Summary

Applications Architect @ Arteris IP Solutions Architect @ Arteris IP San Francisco Bay AreaPrincipal SoC Engineer @ Wave Computing From June 2019 to November 2019 (6 months) Campbell, CaliforniaSenior Design Engineer @ Marvell Semiconductor • Designed, micro-architected and integrated several logical/functional SoC units, determined different power domains based on application in multiple ultra-low power chips• Integrated multiple third party IPs such as ARM’s Cortex-M7, QoS blocks, multiple Synopsys designware blocks, various ARM support system blocks, bus arbiters and memory wrappers• Implemented low power design methodologies such as clock gating, power gating, Dynamic Voltage & Frequency scaling(DVFS) scheme and categorizing multiple power domains used in sleep/deep-sleep modes• Supported various post-silicon validation activities such as board bring up, leakage current/voltage measurements, electrical pad characteristics and validating low power functionalities in SOC From November 2014 to January 2016 (1 year 3 months) San Francisco Bay AreaIC Design Engineer 2 @ LSI, an Avago Technologies Company • Micro-architected, designed and supported major RTL blocks at IP and SoC level within the I/O Controller Core over three chip generations• Proposed, implemented and optimized design feature to I/O Controller core and implemented in collaboration with the architect resulting in a 20% performance improvement• Collaborated with Firmware, Systems engineering and Product integration teams to propose new change requests, performance enhancements based on customer feedback and issues• Worked with the backend and FPGA teams to overcome issues related to timing violations, exceeding power budgets, CDC violations, Lint and Structural Errors at IP and SoC levels• Verified I/O Controller Core of Raid-On-Chip (ROC) design using directed/random-seed based simulations, assertions using a coverage driven UVM test bench From October 2010 to November 2014 (4 years 2 months) Colorado Springs, Colorado AreaResearch Assistant @ University of Southern California • FPGA Implementation of the Intel’s Pentium 4 NETBURST architecture in the Tomasulo processor which is 4 way superscalar comprising of various blocks such as Register Alias Table (RAT), Physical Register File, Free Register List (FRL), Reorder Buffer (ROB) with aggressive register reclamation from Free Register list, Return Address Stack (RAS)• Simulated and synthesized the above processor in VHDL using ModelSim and Xilinx Tool under Prof. Gandhi Puvvada From June 2009 to May 2010 (1 year) Greater Los Angeles AreaSoftware Engineer @ Keane • Prepared Business Intelligence reports using IBM’s Cognos 8.2 Reporting Tool, Created Extract Transform and Load (ETL) jobs using IBM’s Data Stage v7.5 ETL Tool• Part of a team which performed coding, requirement analysis, development of Data Stage jobs (ETL) and maintained processes of software development• Wrote test cases in order to check the integrity of the data in the reports and ETL jobs. Acted as Quality Team Leader in the process of delivering the code to the client From June 2007 to July 2008 (1 year 2 months) Bengaluru Area, India

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In a nutshell

Mohan Krishnareddy's Personality Type

Introversion (I), Intuition (N), Thinking (T), Judging (J)

Average Tenure

1 year(s), 7 month(s)

Mohan Krishnareddy's Willingness to Change Jobs



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