Ming-tsun Hsieh’s Email & Phone

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Ming-tsun Hsieh

Sr. Staff Digital Design Engineer @ IDT - Integrated Device Technology, Inc.

Ming-tsun Hsieh Contact Details

Location:
San Francisco Bay Area
Work:
Sr. Staff Digital Design Engineer @ IDT - Integrated Device Technology, Inc.
Senior Principal Engineer, SSD ASIC Design @ Western Digital
Staff Engineer @ Huawei Technologies USA
Education:
MS, Electrical Engineering @ New York University
About:

RTL design and verification engineer with hands-on experience in ASIC front-end design activities, including micro-architecture specification, RTL coding, verification (testbench development, testcase generation, and test regression), logic synthesis, scan insertion, ATPG, logical equivalency check and static timing analysis. Specialties: Verilog, SystemVerilog, Perl, Tcl, C/C++, VCS, Design Compiler (DC), DFT Compiler, TetraMax, Formality and PrimeTime. Domain knowledge: UART/SPI/I2C, 

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