Strong technical background in semiconductor devices, circuit modeling, design, and technology. Led successful engineering teams to provided models, tools, methodology, infrastructure, and company-wide support for much of the digital design flow.

Principal Engineer @ Analog modeling and Verification From August 2015 to Present (5 months) Verification Engineer @ Verification implementation for read channel ICs using OVM/UVM methodologies. Analog behavioral models using SystemVerilog construct. From May 2014 to August 2015 (1 year 4 months) Allentown, Pennsylvania AreaVerification Engineering @ Analog/Mixed-signal behavioral modeling From 2008 to August 2015 (7 years) Adjunct lecturer @ Teaching semiconductor device physics part-time From January 2012 to May 2012 (5 months) Senior Technical Manager @ From April 2007 to 2008 (1 year) Technical Manager @ From September 1999 to April 2007 (7 years 8 months) MTS @ From 1996 to 1999 (3 years) MTS @ From 1988 to 1996 (8 years) Senior Technical Associate @ From 1979 to 1983 (4 years)

Ph.D., Electrical Engineering @ Princeton University From 1983 to 1988 B.S., Physics @ Fairfield University From 1975 to 1979 Kevin Stiles is skilled in: SoC, VLSI, Semiconductors, Integrated Circuit Design, ASIC, CMOS, Analog, EDA, Electrical Engineering, Verilog, Electronics, Simulations, Mixed Signal, FPGA, Perl