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Jingying Xiao

Sr ASIC Design Verification Engineer @ AMD

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Toronto, Canada Area
Sr ASIC Design Verification Engineer @ AMD
ASIC Design Verification ENGINEER @ AMD
Design verification infrastructure engineer @ AMD

ASIC PM/PG ENGINEER @ Power Management and Power Gating verification at system level From September 2011 to Present (4 years 2 months) Design verification infrastructure engineer @ Bring up system-level power-gating verification flow. Maintain and monitor low-power verification automation flow. Program in: C, C++, Verilog, System Verilog, Perl, Ruby. Work with EDA tools: VCS, MVSIM, MVRC, and 

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