Jens Haetty's Email

Senior Engineering Manager @ From July 2015 to Present (3 months) East Fishkill / Albany NYSenior Engineering Manager - Advanced Bitcell Solutions @ Leading an awesome team of 10 SRAM Bitcell Developers and Layout Engineers who deliver advanced, competitive, manufacturable, and high quality SRAM bitcell solutions in order to enable leadership for IBM systems and OEM clients, and to generate high value for IBM's technology offering, consistent with the needs of our Server, OEM, and Development Alliance business. Our mission includes to broadly collaborate across technology and design teams to optimize yield, leakage, and performance, and to meet project milestones and to ensure a successful ramp in manufacturing. We also support technology qualifications through timely definition of SRAM device centering for qualification hardware, the definition of qualification plans and test conditions, as well as driving root cause analysis of soft bit fail populations at wafer and package level. Our current scope are planar and FINFET based SRAM cells down to currently 7nm. From September 2012 to June 2015 (2 years 10 months) Seoul, Korea / East Fishkill, NY20nm/14nm SRAM Characterization / IBM Assignee at Samsung Korea @ - Interface between IBM and Samsung for 20nm planar HKMG and 14nm FINFET SRAM yield ramp. - Embedded in Samsung's NRD Integration Team - Responsibilities include SRAM yield learning methodology, yield ramp, and pareto definition. From September 2011 to September 2012 (1 year 1 month) Seoul, Republic of KoreaManager SRAM/eDRAM Functional Characterization @ Managed a highly motivated and cross-cultural / cross-company team of 11 IBMers and 9 Alliance Partner (Samsung, Global Foundries, ST Micro) engineers. Our technology scope ranged from 45nm down to 20nm bulk and SOI. Our mission included: - Provide functional characterization reporting for new technologies to improve yield, performance and reliability. - Deliver yield paretos of key defect mechanisms and drive closure on same with the technical community - Deliver timely, accurate identification of trends (with vintaging, tool analysis, etc) to assist in root cause analysis. - Identify and summarize key statistics and trends. - Characterize window/trade-offs between stability and performance - Establish/Leverage Early Product Yield Learning vehicle(s) in preparation of their transfer to manufacturing - Support the qualification activities and technology milestones - Work with integration and process module teams to provide timely feedback on split/process experiments, tool quals, etc. - Deliver test times which are consistent with development test volume and capacity. - Provide MFG and DEV/Test Site RIT setups ahead of 1st silicon. - Drive ILT productivity through test time reduction efforts in functional test; - Deliver high quality functional test programs, test characterization and analysis. - Meet or exceed customer's expectations for inline functional test pnp's, functional yield characterization, and driving failure analysis activities. - Meet required business objectives including budget,ISO 9000, ISO 14000, safety and security. - Develop and implement a test/characterization/yield strategy that supports technology development of MD advanced SRAM/logic/efuse/eDRAM. - Investigate and resolve all test data accuracy issues. - Maintain high "first-time right" metric for new test programs; ensure proper validation standards for all aspects. From November 2007 to September 2011 (3 years 11 months) Advisory Engineer, 300mm Manufacturing and ASIC IP Qualifications @ • Functional process and design characterization of 45nm SRAM technology, in collaboration with Samsung, Infineon, Chartered, and Freescale. • Responsible lead engineer for the qualification of 90nm ASICs base library offerings such as embedded DRAM, SRAM, TCAM, digital and analog cores (PLL, HSS, etc.). • Yield monitoring and learning for 130nm and 90nm ASIC test sites and customer parts, in close collaboration with design, process integration, device design, and test. • Development and programming of SAS-based web-reporting tools for engineering and manufacturing support. • Departmental ISO representative. From February 2005 to October 2007 (2 years 9 months) Staff Engineer - Product Test Development @ • Team Leader FE (Wafer Test) Test Group. Member of Wafer Test Expert Team. • Program Development for DDR 1G/110nm, DDR 512M/110nm, DDR 512M/140nm, on T5571 and T5375. Responsible for the implementation of ATL Test Plan and ALPG code, test time reduction road map, definition and documentation of test conditions and product characterization, development and implementation of high-parallel wafer test solutions. In this function, 512M/110nm achieved company-wide leadership in executing the TTR roadmap. Successful transfer and implementation of BE and APT test coverage in FE. • Electrical wafer-level characterization of DRAM designs on manufacturing test systems (Advantest). • Member of first Self-Assessment Team for DNV/ISO-9000 certification 2002/2003. Identified action items for Product Test Group and implemented measures to address those for successful certification. • Conducted training on topics such as tester and prober control, cryogenic materials handling, and wafer and module test methodologies. From January 2001 to February 2004 (3 years 2 months) Test Engineer - DRAM Development Alliance (IBM/IFX/Toshiba) @ • Owner of the wafer test flow. Contributed as such extensively to the 256M qualification (“PPQ”) of 256M SDR and DDR SDRAM volume products based on 200nm and 175nm technology, and to the pre-qualification (“PPQR”) of 256M (150nm). • Developed several test packages on TERADYNE for design analysis and margin characterization, resulting in a faster feedback after 1st silicon. • Headed and designed several process window analyses to correlate DC performance, signal development, retention and timing margins to process and device parameters on 175nm and 150nm technologies. • Closely collaborated with device designers, circuit designers, and data analysis teams from IBM and Infineon regarding design analysis, design-for-test, and test coverage issues. From July 1998 to December 2000 (2 years 6 months) PFC, 1st Staff Company, 123rd Tank Battailon @ Radio Operator, Cable Monkey, Member of the Liaison Team to the Castle Martin Training Range, Castle Martin, Wales, UK. From October 1987 to December 1988 (1 year 3 months) Amberg, Germany

Ph.D., Physics @ University at Buffalo From 1992 to 1998 M.A.., Physics @ University at Buffalo From 1992 to 1993 Vordiplom, Physics, Chemistry @ The Julius Maximilians University of Würzburg From 1989 to 1991 Jens Haetty is skilled in: CMOS, Semiconductors, ASIC, Thin Films, EDA, IC, Failure Analysis, Characterization, SoC, Simulations, Semiconductor Industry, Silicon, Integration, Yield, Process Integration, SRAM, Testing, DRAM, Analog, Materials Science, Design of Experiments, Manufacturing, Embedded Systems, Engineering Management, Management, Microprocessors, Mixed Signal, Team Leadership, Circuit Design