Jaehyup Kim’s Email & Phone

Jaehyup Kim Contact Details

San Diego, California, United States
Senior Engineer @ XRONET
Principal Engineer @ Samsung Electronics
Mixed Signal Design Engineer @ Qualcomm
MS, Electrical Engineering @ Korea Advanced Institute of Science and Technology

Senior Engineer @ 1. 28nm Digital PLL IP 2. 14nm/20nm Calibrated Delay Circuit (CDC) IP for DDR interface From June 2012 to Present (3 years 7 months) Internship @ 1. Secondary ESD Buffer - To protect ESD from the interface between the analog and the digital block 2. Operational amplifier for PLL loop filter From October 2011 

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