Ronen Paz's Email & Phone Number

ASIC/FPGA technical lead

December 2020 to Present

FPGA design expert

January 2020 to January 2021

Noveto

FPGA & ASIC technical leader

September 2019 to January 2020

Intel Corporation

Mixed Signal, VLSI, RTL Design & Verification, Emulation on FPGAs.

January 2015 to January 2019

FPGA/ASIC Expert

January 2011 to January 2015

FPGA design expert.

January 2008 to January 2011

VLSI FPGA ASIC

January 2003 to January 2008

ASIC designer

January 2002 to January 2003

Head of hardware and validation department and labs.

January 2001 to January 2002

Motorola Semiconductor

DSP/VLSI engineer, DFT expert

January 1997 to January 2000

Expert of ASIC development as external advisor

Expert of ASIC development as external advisor

January 1993 to January 1997

i sight

UNIX System Administrator & VLSI/ASIC engineer(IT)

January 1990 to January 1992

Intel

Analog/Circuit VLSI Engineer, STA

January 1987 to January 1990

Intel Corporation

mixed signal, hi speed and low power digital design, FPGA Emulation.