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Ibrahim Almohandes

Principal Software Engineer

Principal Software Engineer at Roche Sequencing Solutions

San Francisco Bay Area

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Ibrahim Almohandes's Email Addresses & Phone Numbers

Ibrahim Almohandes's Work Experience


Principal Software Engineer

Santa Clara, CA

EPAM Systems at Google

Senior Software Engineer

July 2017 to September 2017

Mountain View, CA

Intel Corporation

Senior Software Engineer Contract

March 2017 to June 2017

Folsom, CA

Ibrahim Almohandes's Education

University of Waterloo

PhD, Electrical & Computer Engineering

2000 to 2005

Ain Shams University

M.Sc., Electrical Engineering

1996 to 1998

Al-Azhar University, Cairo, Egypt

B.Sc., Systems and Computer Engineering, GPA: 3.2/4.0

1989 to 1994

Ibrahim Almohandes's Professional Skills Radar Chart

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Strong sense of self

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Ibrahim Almohandes's Estimated Salary Range

About Ibrahim Almohandes's Current Company


Principal Software Engineer (Python) at Roche Sequencing Solutions.

Frequently Asked Questions about Ibrahim Almohandes

What company does Ibrahim Almohandes work for?

Ibrahim Almohandes works for Roche

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Ibrahim Almohandes is Principal Software Engineer

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About Ibrahim Almohandes

📖 Summary

Principal Software Engineer @ Roche Principal Software Engineer (Python) at Roche Sequencing Solutions. Santa Clara, CASenior Software Engineer @ EPAM Systems at Google Software Engineer Contract at Google. From July 2017 to September 2017 (3 months) Mountain View, CASenior Software Engineer Contract @ Intel Corporation Develop object-oriented content (in C++) for Intel’s LLVM-based system validation compiler (Maestro). Understand protocol specifications to develop device library and concurrency content for Intel’s platforms and devices. Port Python code into C++. Use Git for revision control; Gerrit for code review; and Linux as software development platform. From March 2017 to June 2017 (4 months) Folsom, CASenior Software Engineer @ Lattice Semiconductor - Object-oriented design and C++ cross-platform (Windows/Linux) development, of EDA applications that are part of the Lattice Diamond FPGA design software, including: Backend Annotator that converts the full-chip design into Verilog/VHDL plus SDF files (for backend functional/timing verification); and Module Generator that allows user to customizes PCS/Serdes IP blocks into Verilog or VHDL format.- Developed C++ APIs and tools for supporting the IEEE-P1735 encryption/decryption standard, using the OpenSSL open-source libraries; fully implemented the standard despite of the minimal info at hand (a white paper with no access to the original IEEE draft), and verified the solution by reading the encrypted files into the industry-standard simulation tools.- Wrote C++ APIs for parsing timing constraints (SDC) files by the Lattice Synthesis Engine (LSE), as well as APIs for the LSE Schematic Viewer and Netlist Analyzer.- Developed scripts in Perl, UNIX shell scripts, and Windows batch files for use in: automation of library watermarking/encryption processes, and synthesis header-file generation (during the daily software build). Created TCL user commands for end-users to easily compile Lattice library simulation models.- Enabled programming/configuration features of a new FPGA device in the deployment tool. Pre-silicon verification (in a Linux emulation environment) of the device’s bitstream configuration operations (written as SVF commands).- Applied code coverage, using gcov, to reduce C++ code redundancy by more than 40% in some modules.- Received various Relay Awards for contribution to achieving critical milestones, for quick resolution of key customer as well as internal blocker issues, and for going beyond current responsibilities to support new features. Received Sprint Award for providing a key training to Lattice contractors. From January 2012 to October 2015 (3 years 10 months) San Jose, CASoftware Engineer @ Lattice Semiconductor - Software development, in C++, of the backend-annotation tool; coding parts of the IPExpress module generator.- Developed a tool, in Java, that automates watermarking of OEM simulation libraries, during which the tool automatically sends/receives e-mails to/from the simulation vendor (as part of the daily software build).- HDL modelling of Lattice FPGA device simulation libraries. Functional/timing verification and debugging of Verilog / VDHL library models as well as customer designs.- Applied run time analysis, using IBM Rational PurifyPlus, to discover and eliminate memory leaks and bottlenecks in the C++ code, hence enhancing the back-annotator performance by about 30%.- Received multiple Spot Awards for contributing to major milestones, and for taking initiative. From October 2005 to December 2011 (6 years 3 months) Bethlehem, PAResearch Assistant, VLSI Group, Electrical & Computer Engineering Dept. @ University of Waterloo - RTL design of an energy-efficient turbo decoder for 3G wireless terminals; FPGA prototyping (on a Xilinx Virtex-II) and testing of the turbo codec (with an ARM Integrator board).- Algorithm modelling, simulation, and synthesis, using Matlab, C, and VHDL. Grad courses studied include: Introduction to Optimization, and Computer Network Security.- Worked as TA for: Programming Languages and Translators, Algorithms and Data Structures, Real-Time Operating Systems, and Computer Structures. Also (as a TA), wrote shell scripts for auto-marking, completed Java and Prolog programming assignments, and developed C-like test processes for an RTOS project. From January 2000 to August 2005 (5 years 8 months) Waterloo, Ontario, CanadaJava and Internet Developer @ MindWork Middle East - Developed Java components for an eBusiness project, using Sun’s JDK/JDBC and SQL, as part of a web application hosted on an IBM WebSphere server.- Built an Intranet-based customer database system, using MS InterDev, ASP/VBScript, JavaScript, and MS Access.- Performed web authoring using HTML/FrontPage; provided technical support; maintained and administered the company’s LAN; communicated with the headquarters in Vienna, Austria; and participated in local market research and discussions. From July 1998 to December 1999 (1 year 6 months) Cairo, EgyptResearch Assistant, Systems & Computer Engineering Dept. @ Al-Azhar University • VHDL synthesis, simulation and physical design of DLX RISC processor with Mentor Graphics tools; ALU section was fabricated (in CMOS technology); ASIC chip was tested successfully.• TA duties: Mathematics, Electric/Electronic/Logic Circuits, Microprocessors, Computer-Based Control; Labs supervised/tutored: VHDL, C/C++, DBase, MS Windows, desktop applications. From January 1996 to June 1998 (2 years 6 months) Cairo, Egypt

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Ibrahim Almohandes's Personality Type

Extraversion (E), Intuition (N), Feeling (F), Judging (J)

Average Tenure

2 year(s), 10 month(s)

Ibrahim Almohandes's Willingness to Change Jobs



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