Digital Design Engineer, Mixed Signal Products @ • Digital design for high speed ADCs and DACs • Architectural design, logic design, RTL implementation, verification • Synthesis • Design for test (DFT) • Physical design • Static timing analysis (STA) From April 2014 to Present (1 year 9 months) Digital Design Engineer, Communications Infrastructure (Graychip) @ • Development, verification, and bring up of the TCI6630K2L (Lamarr) digital radio front-end SoC targeted for small cell wireless infrastructure markets • Designed, implemented, and verified numerous digital logic circuits including signal processing blocks, filters, mixers, test signal generation, clock gating, interfaces, FIFOs, encoders/decoders, interrupts, synchronization, measurement, system control • Owned the IP development and functional verification of the JESD204B SERDES-based interface, supported integration into several chips across TI's portfolio (see projects) • Managed the system model for all blocks in the digital front-end (DFE) • Responsibilities include RTL development, systems modeling, microarchitecture, synthesis, FPGA system design for R&D, UVM test bench, chip bring up, chip characterization, design flow scripting, technical documentation, project management, applications engineering support From June 2010 to April 2014 (3 years 11 months) Intern, Communications Infrastructure (Graychip) @ • Designed, implemented, and verified the Serial Peripheral Interface (SPI) bus for the GC5330 wideband digital front-end (DFE) transceiver (see projects) • Developed a Universal Host Port Interface (UHPI) on an FPGA platform for high speed data transfer with C67xx DSPs From May 2009 to August 2009 (4 months) Embedded System Design Consultant @ • PCB schematic design, layout, and assembly of an embedded solution for a Power over Ethernet (PoE) regulator with military specifications used in network sensor devices in the Chemical Biological Protective Shelter (CBPS-M4A) • Rigged a full-scale test bench to evaluate power delivery and consumption and communication From May 2008 to August 2008 (4 months) Electrical Engineering Intern, Battery Management Solutions @ • Built a Visual Basic software package to conduct automated testing and upgrading of smart battery monitoring firmware (ti.com/battery) From June 2007 to August 2007 (3 months) Electrical Engineering Co-op, Cell Processor @ • Performed physical verification of the Sony Toshiba IBM (STI) Cell Processor (the chip in the Sony PlayStation 3) • Conducted synthesis and place-and-route for the I/O Controller • Conducted design rule checks (DRCs) including power, electromigration, and noise interference • Created help documentation and trained two senior engineers as replacements From May 2005 to December 2005 (8 months) Intern and Manager @ Dec 2003 – January 2004 (2 months) | Houston, TX June 2003 – August 2003 (3 months) | Houston, TX June 2001 – August 2001 (3 months) | Houston, TX • Developed an ASP/SQL/MS Access web application for managing the nation-wide scheduling of company trainers with automated e-mail correspondence between trainers and customers • Wrote custom Visual Basic scripts for new customers transitioning from other software platforms to convert their SQL databases for compatibility with HCSS software • Created an internal employee evaluation system with Visual Basic and MS Access • Managed a team of interns during the last internship From June 2004 to August 2004 (3 months) Teaching Assistant, Math @ • Helped students work problem sets and graded papers From August 1999 to May 2000 (10 months)

MS, Electrical Engineering @ University of Southern California From 2008 to 2010 BS, Electrical Engineering @ The University of Texas at Austin From 2003 to 2008 International Baccalaureate From 2001 to 2003 Geo Tu is skilled in: FPGA, VLSI, IC, Verilog, Circuit Design, Signal Processing, Photography, C, C++, Computer Architecture, Electrical Engineering, Digital Electronics, Matlab, Mandarin, Portrait Photography