I am self-motivated , hardworking , responsible ,determined towards my goals , who would like to face challenges , learn new ideas and technologies .I like productive work and my interests are to improve my skills to the best .

DFT Design Engineer @ MBIST: -> Check controlability of Memory clocks and resets. -> Plan for Embedded logic generation with trade off of area , time ,power . -> Generate and Insert the logic and trace the test pins to toplevel . -> Verify the logic at RTL , post -synthesis ,post-Layout . IOMUXING: -> Plan for the pins to be shared . -> Generate the logic . -> Hookup the pins from core to iomux logic and iomux logic to top level pins . JTAG Mixed: -> Enable the power pins and configure the pad lib. -> Trace the pads till top . -> Plan for the Embedded logic . -> Generate and insert the logic . -> Trace the test pins till top level. -> Verify the logic at RTL, post-synthesis , post-layout. SCAN : -> Pass the DRC at most . -> Insert Scan/EDT logic and synthesize the embedded_logic . -> Generate patterns and analyze the coverage drop if required. Automation: Automated MBIST insertion config files for LV and Cadence tool using perl for multiple blocks . -> Inputs : Excel sheet -> Outputs: Configuration file Simulation : -> Notiming and Timing in NCSIM . From August 2012 to Present (3 years 5 months) DFT Design Engineer @ As a DFT Engineer my responsibilities are DFT implementation , simulations , final checks . (MBIST,BSCAN ,SCAN , ATPG , simulations , NCSIM , VCS , IOMUXING , SOC ) From August 2012 to Present (3 years 5 months)

Bachelor of Technology (B.Tech.), Electronics and Instrumentation Engineering, A @ Pydah Engineering College From 2007 to 2011 Intermediate, MPC @ Sri Chaitanya Kalasala From 2006 to 2007 Schooling @ Vignan Vidhyalayam From 2004 to 2005 Schooling @ Kendriya Vidyalaya From 1995 to 2003 Gautami Palikila is skilled in: RTL Design, Perl, NCSim, Verilog, Tessent MBIST, Tessent BSCAN, Perl Scripting, RTL Compiler, TK, Simulations, VLSI, ASIC, Cadence, Scan, SoC, FPGA, Testing