Senior Circuit Design Engineer with 11 years experience from project conceptualization, architecture/circuit design, pre- and post-silicon validation to customer support. Very well-rounded in terms of digital and analog design methodologies. • Circuit Design from concept to validation. • Circuit and Logic Verification in all aspect. • FPGA Expert : VHDL / Verilog Advanced knowledge: • PLL Validation, Static Timing Analysis, Mix signal simulations, Matlab, Image Processing HDL knowledge: • Verilog, SystemVerilog, Verilog-A, VHDL, ABEL. Advanced Language: • Python, Perl, Bash, TCL, C, HTML etc'.

Circuit Designer / Verification Engineer @ From November 1997 to March 2009 (11 years 5 months)

MBA in Finance, Business Administration @ Bar-Ilan University From 2008 to 2010 FPGA Expert & VHDL @ Logtel From 2009 to 2009 M.Sc, Computer & Electrical Engineering @ Ben-Gurion University of the Negev From 2005 to 2007 B.Sc, Computer Engineering @ Technion - Israel Institute of Technology From 1994 to 1998 "Yavne"John Bryce Eyal Hartmann is skilled in: SoC, ASIC, VLSI, SRAM, Memories, Circuit Design, Verilog