Over 25 years experience in the computer field in many disciplines including: ASIC and FPGA design verification, and silicon verification, RLT simulations, and gate simulations. Areas of expertise include verification of SoC designs, and mixed signal chip verification, development of Board Support Packages for customers, and designing and implementing device drivers for Linux and other RealTime operating
Over 25 years experience in the computer field in many disciplines including: ASIC and FPGA design verification, and silicon verification, RLT simulations, and gate simulations. Areas of expertise include verification of SoC designs, and mixed signal chip verification, development of Board Support Packages for customers, and designing and implementing device drivers for Linux and other RealTime operating systems. Have designed and implemented SystemVerilog Test Benches with continuous assertions and coverage groups on eight projects and five of them used UVM design and libraries with the implementation.
Design Verification (consultant) @ The task performed was to run all current gate-sims on a new product that was a copy of the earlier design but with fewer capabilities. Added to and corrected the failing test. Then generated the test patterns for ATE. From July 2013 to Present (2 years 6 months) Design Verification Engineer @ Worked on verification of a LPDDR2 PHY. Started with a partial UVM test bench. Finished the TB and added two new OVCs, added SV asserts connected to PHY block internal wires, a bench scoreboard, and constrained random tests. The testing verified clocking and all phase/delay of data inputs and outputs. Included the incorporation of several manufacturers and Denali memory models in the TB. Included a virtual sequencer for stress and random reset testing. The TB also included coverage and coverage reports. Wrote a Test Plan and Test Procedures documents. All tests were written in SystemVerilog using strict adherence to UVM standards. From February 2013 to August 2013 (7 months) San Francisco Bay AreaDesign Verification Engineer @ The first task performed was to design a UVM test bench with all of the needed OVCs and interface and transaction packets that would be needed. Then with the assistance of two other test engineers was to take the existing System Verilog test bench and. Worked on verification of Clause 37, 72 & 73 and training on a new larger version of the original chip. The original could interface with only 4 lanes of traffic and the new version has a total of 12 lanes and can switch interfaces at up to 127 giga-bits per second. The original tests needed to be modified so that all lanes were tested. Tests were all written in System Verilog. From July 2012 to January 2013 (7 months) San Francisco Bay AreaDesign Verification Engineer @ Worked on verification of the X-BOX designer interface card. This product ran on an FPGA and was an interface between the X-BOX console and the display monitor. It worked as a capture device that took the outputs of the workstation and saved them in local memory before sending them out to the display monitor. I verified a portion of the FPGA that wrote to the DDR and QDR memories. The tests were designed to run in a simulation environment and then when the boards and FPGA were ready the tests were expanded to test more functions and to run over the entire memory space. Tests were coded in C++. From May 2012 to September 2012 (5 months) San Francisco Bay AreaDesign Verification Engineer @ Worked on verification team to first write a test plan and test design to verify IEEE-802.3 Clauses 36, 37, 72, 73, and 82. The Test bench was developed in India and I added the clause 72 model to this Test Bench. The Denali model was not adequate for testing the entire test conditions needed. Developed the CL72 tests and ran them in simulation. Worked out errors found with the ASIC Design Engineering team to modify the RTL to correct the errors found. Using coverage on tests was able to get the 98.7% RTL test coverage. The tests were all written in System Verilog. Also worked closely with the other Design Verification team testing the other clauses that were put into the Test Plan and aided in the development of some of those tests as well. From January 2012 to May 2012 (5 months) San Francisco Bay AreaDesign Verification Engineer @ Worked on verification team to verify the design of the Clock Control, Power Management, LED, and Video blocks for a smart-phone chip with a DSP, A9 and R4 Cortex processers. Designed and implemented the test bench using UVM and built the UVCs around the blocks that needed to be tested in a stand-alone test suite. UVCs were designed and implemented as small drivers in System Verilog that were able to be moved to system-level verification testing with minimal modification on simulations, Chip-it multi-FPGA emulator, and then used for silicon verification for block and multi-block stress tests. Responsible for design and implementation of test that drove data on buses and to all peripheral to test the power consumption and peripheral clock gating. The drivers that I wrote included the three processers, LED, Display Processor Engine, Graphics Engine, and Audio Codec. Used PerForce for code repository. Tests were written in System Verilog and includes and the macros in ANCI C. From January 2011 to December 2011 (1 year) San Francisco Bay Areaconsultant @ From 2000 to 2011 (11 years) Design Verification Engineer @ Worked on verification team to verify the design of the Bus-Matrix block for a smart-phone chip with a DSP, ARM11, and Cortex processers. Tests were built as small drivers to be run in RTL simulations, on an FPGA (ChpIt & Pladium), and then used for silicon verification. Responsible for design and implementation of test that drove data on all of the 14 Bus Masters to the 12 Slave ports. The Maters included the three processers, DMA, Display Processor Engine, Graphics Engine, and Audio Codec. The Bus Matrix Block had priority settings and performance counters that had to be tested and that all Master ports could be run concurrently and validate that all of the data was moved correctly. Used PerForce for code repository. From February 2009 to December 2010 (1 year 11 months) San Francisco Bay AreaDesign Verification Engineer @ Took the ASIC Design Verilog and converted to a Xilinx multi-FPGA to test the WiMax ASIC design and give the software team the ability to exercise their WiMax software. The board had the Qualcomm processor and this interfaced to the three FPGAs on the board. Helped the software engineers load and test their software and debugged the FPGA with it. Several errors in the ASIC design were found and reported to the hardware design team for correction. The RF was not included in the ASIC Design Verilog and drivers to interface to the FPGA were developed and an Ethernet input was used to send and receive data from the FPGA. A data generator and monitor for that interface was developed that allowed the software engineers to interface quickly to send and view received data from the hardware interface to their software and back again. From April 2008 to December 2008 (9 months) Greater San Diego Areasoftware engineer @ From 1990 to 1992 (2 years)
Doctor of Philosophy (PhD), Electrical and Electronics Engineering, 4.0 @ Massachusetts Institute of Technology From 1974 to 1975 Master's degree, Electrical and Electronics Engineering, 4.0 @ University of Minnesota-Twin Cities From 1968 to 1970 Bachelor's degree, Mathematics @ University of Berlin From 1966 to 1968 E. Rabinowitz is skilled in: Software Development, ASIC Design Verification using UVM, ASIC Design Verification w/SystemVerilog continuous assertions, FPGA Design Verification, ASIC Design Verification w/ coverage groups, Board Support Package, Device Drivers, Simulation Software, Agile Methodologies, XML, SystemVerilog, C#, Verilog, SQL
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