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San Francisco Bay Area
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Over 10+ years of experience in IC package design, simulation and verification. Wirebond, PoP and flip chip packages Stacked die and SoC Power Integrity and Signal Integrity experience

Sr Staff Package and Signal Integrity Engineer @ Design flip chip packages for SSD controller using 3rd party IPs(SERDES, DDR and Flash) and run Signal and Power Integrity simulations using 

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