Experience with EDA Tools and Design Flows:
Physical Design Flow: Specification > Leaf Cell Design > DRC > Characterization
- Layout Editor: Cadence Virtuoso XL, Magic VLSI Layout Editor.
- Characterization: Cadence HSpice Circuit Simulator
- DRC: Mentor Graphics Calibre, Magic DRC
RTL to GDSII Design Flow: RTL > Synthesis > Place & Route > Timing and Power Analysis
- HDL: SystemVerilog, Verilog, VHDL.
- Lint & CDC: Mentor Graphics Questa
- Low Power Optimization: Calypto PowerPro
- Formal Verification: Cadence IEV
- RTL, Post Synthesis and Post Layout Simulation: Mentor Graphics ModelSim, Cadence NCSim
- RTL Synthesis: Synopsis Design Compiler, Cadence RC
- Power Analysis & Timing Closure: Synopsys Primetime-PX
- Place & Route: Cadence SoC Encounter
- Scripting: TCL, Python
RTL to FPGA Design Flow: RTL > Synthesis > FPGA Implementation > Testing
- Altera Specific Tools: Altera Quartus II, NiOS II EDS, SoPC Builder
Hardware Design Engineer (IMGWorks Verification Platforms / Testchips) @ - RTL Development for test chips
- Power Analysis
- Gate Level Simulation From April 2014 to Present (1 year 9 months) Graduate Hardware Design Engineer (IMGWorks Verification Platforms / Testchips) @ - RTL Development for test chips
- Power Analysis From January 2013 to April 2014 (1 year 4 months) Watford, United KingdomVisiting Researcher @ Project Name: StrokeBack
- Machine Learning
- Data Analysis using Matlab
- Classification of activities of daily living using various classifiers e.g. SVM, libSVM, LDA, QDA, kNN. From October 2012 to December 2012 (3 months) Southampton, United KingdomGraduate TME @ - Developing application specific product selection guides.
- Writing Technical Articles for quarterly published technology journals.
- Engaging with suppliers to maintain an up-to-date knowledge base on product roadmap and NPI.
- Developing and demonstrating compelling product demos at key events (e.g. Electronika 2010). From July 2010 to September 2011 (1 year 3 months) Leeds, United KingdomApplication Engineering Intern @ - Understanding the key concepts of Silicon Technology behind Intel’s 45 nm process technology.
- Developing demo kits; to portray the benefits of CoreTM μArchitecture to potential end customers.
- Benchmarking and Competitive Analysis of Intel Server Products using industry standard benchmark suites. Notable analysis included: Intel Xeon and Intel 82598 10 Gbit Ethernet Adapter.
- Achievements and Recognitions: Recipient of Intel EMEA Recognition Award for significant
contribution towards team’s success. From 2007 to 2008 (1 year) Swindon, United Kingdom
MSc, System on Chip (SoC), Distinction @ University of Southampton From 2011 to 2012 BEng, Electronic and Communications Engineering, First Class (Hon.) @ University of Leeds From 2005 to 2009 Computing Studies (A Level)Computing Studies (A Level)Computing Studies (A Level)ESS Ahmed Rahim is skilled in: Digital IC Design, Physical Design, Place and Route, Standard Cell Lib Design, Synopsys Design Compiler, Cadence Virtuoso, Cadence SoC Encounter, Synopsys Primetime, Synopsys DFT Compiler, SoC, Synopsys tools, Logic Synthesis, Matlab, Classification and Machine Learning, Weka
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